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57 lines
1.7 KiB
57 lines
1.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* arch/sh/kernel/cpu/sh2a/probe.c |
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* |
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* CPU Subtype Probing for SH-2A. |
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* |
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* Copyright (C) 2004 - 2007 Paul Mundt |
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*/ |
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#include <linux/init.h> |
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#include <asm/processor.h> |
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#include <asm/cache.h> |
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void cpu_probe(void) |
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{ |
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boot_cpu_data.family = CPU_FAMILY_SH2A; |
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/* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */ |
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boot_cpu_data.flags |= CPU_HAS_OP32; |
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#if defined(CONFIG_CPU_SUBTYPE_SH7201) |
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boot_cpu_data.type = CPU_SH7201; |
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boot_cpu_data.flags |= CPU_HAS_FPU; |
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#elif defined(CONFIG_CPU_SUBTYPE_SH7203) |
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boot_cpu_data.type = CPU_SH7203; |
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boot_cpu_data.flags |= CPU_HAS_FPU; |
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#elif defined(CONFIG_CPU_SUBTYPE_SH7263) |
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boot_cpu_data.type = CPU_SH7263; |
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boot_cpu_data.flags |= CPU_HAS_FPU; |
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#elif defined(CONFIG_CPU_SUBTYPE_SH7264) |
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boot_cpu_data.type = CPU_SH7264; |
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boot_cpu_data.flags |= CPU_HAS_FPU; |
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#elif defined(CONFIG_CPU_SUBTYPE_SH7269) |
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boot_cpu_data.type = CPU_SH7269; |
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boot_cpu_data.flags |= CPU_HAS_FPU; |
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#elif defined(CONFIG_CPU_SUBTYPE_SH7206) |
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boot_cpu_data.type = CPU_SH7206; |
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boot_cpu_data.flags |= CPU_HAS_DSP; |
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#elif defined(CONFIG_CPU_SUBTYPE_MXG) |
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boot_cpu_data.type = CPU_MXG; |
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boot_cpu_data.flags |= CPU_HAS_DSP; |
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#endif |
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boot_cpu_data.dcache.ways = 4; |
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boot_cpu_data.dcache.way_incr = (1 << 11); |
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boot_cpu_data.dcache.sets = 128; |
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boot_cpu_data.dcache.entry_shift = 4; |
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boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; |
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boot_cpu_data.dcache.flags = 0; |
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/* |
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* The icache is the same as the dcache as far as this setup is |
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* concerned. The only real difference in hardware is that the icache |
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* lacks the U bit that the dcache has, none of this has any bearing |
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* on the cache info. |
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*/ |
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boot_cpu_data.icache = boot_cpu_data.dcache; |
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}
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