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135 lines
2.4 KiB
135 lines
2.4 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (C) 2015 Regents of the University of California |
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* Copyright (C) 2017 SiFive |
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*/ |
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#ifndef _ASM_RISCV_SPINLOCK_H |
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#define _ASM_RISCV_SPINLOCK_H |
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#include <linux/kernel.h> |
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#include <asm/current.h> |
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#include <asm/fence.h> |
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/* |
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* Simple spin lock operations. These provide no fairness guarantees. |
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*/ |
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/* FIXME: Replace this with a ticket lock, like MIPS. */ |
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#define arch_spin_is_locked(x) (READ_ONCE((x)->lock) != 0) |
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static inline void arch_spin_unlock(arch_spinlock_t *lock) |
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{ |
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smp_store_release(&lock->lock, 0); |
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} |
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static inline int arch_spin_trylock(arch_spinlock_t *lock) |
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{ |
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int tmp = 1, busy; |
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__asm__ __volatile__ ( |
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" amoswap.w %0, %2, %1\n" |
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RISCV_ACQUIRE_BARRIER |
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: "=r" (busy), "+A" (lock->lock) |
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: "r" (tmp) |
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: "memory"); |
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return !busy; |
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} |
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static inline void arch_spin_lock(arch_spinlock_t *lock) |
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{ |
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while (1) { |
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if (arch_spin_is_locked(lock)) |
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continue; |
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if (arch_spin_trylock(lock)) |
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break; |
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} |
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} |
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/***********************************************************/ |
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static inline void arch_read_lock(arch_rwlock_t *lock) |
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{ |
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int tmp; |
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__asm__ __volatile__( |
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"1: lr.w %1, %0\n" |
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" bltz %1, 1b\n" |
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" addi %1, %1, 1\n" |
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" sc.w %1, %1, %0\n" |
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" bnez %1, 1b\n" |
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RISCV_ACQUIRE_BARRIER |
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: "+A" (lock->lock), "=&r" (tmp) |
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:: "memory"); |
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} |
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static inline void arch_write_lock(arch_rwlock_t *lock) |
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{ |
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int tmp; |
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__asm__ __volatile__( |
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"1: lr.w %1, %0\n" |
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" bnez %1, 1b\n" |
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" li %1, -1\n" |
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" sc.w %1, %1, %0\n" |
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" bnez %1, 1b\n" |
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RISCV_ACQUIRE_BARRIER |
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: "+A" (lock->lock), "=&r" (tmp) |
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:: "memory"); |
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} |
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static inline int arch_read_trylock(arch_rwlock_t *lock) |
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{ |
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int busy; |
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__asm__ __volatile__( |
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"1: lr.w %1, %0\n" |
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" bltz %1, 1f\n" |
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" addi %1, %1, 1\n" |
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" sc.w %1, %1, %0\n" |
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" bnez %1, 1b\n" |
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RISCV_ACQUIRE_BARRIER |
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"1:\n" |
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: "+A" (lock->lock), "=&r" (busy) |
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:: "memory"); |
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return !busy; |
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} |
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static inline int arch_write_trylock(arch_rwlock_t *lock) |
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{ |
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int busy; |
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__asm__ __volatile__( |
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"1: lr.w %1, %0\n" |
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" bnez %1, 1f\n" |
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" li %1, -1\n" |
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" sc.w %1, %1, %0\n" |
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" bnez %1, 1b\n" |
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RISCV_ACQUIRE_BARRIER |
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"1:\n" |
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: "+A" (lock->lock), "=&r" (busy) |
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:: "memory"); |
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return !busy; |
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} |
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static inline void arch_read_unlock(arch_rwlock_t *lock) |
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{ |
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__asm__ __volatile__( |
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RISCV_RELEASE_BARRIER |
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" amoadd.w x0, %1, %0\n" |
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: "+A" (lock->lock) |
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: "r" (-1) |
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: "memory"); |
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} |
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static inline void arch_write_unlock(arch_rwlock_t *lock) |
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{ |
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smp_store_release(&lock->lock, 0); |
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} |
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#endif /* _ASM_RISCV_SPINLOCK_H */
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