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65 lines
1.6 KiB
65 lines
1.6 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _ASM_RISCV_IMAGE_H |
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#define _ASM_RISCV_IMAGE_H |
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#define RISCV_IMAGE_MAGIC "RISCV\0\0\0" |
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#define RISCV_IMAGE_MAGIC2 "RSC\x05" |
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#define RISCV_IMAGE_FLAG_BE_SHIFT 0 |
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#define RISCV_IMAGE_FLAG_BE_MASK 0x1 |
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#define RISCV_IMAGE_FLAG_LE 0 |
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#define RISCV_IMAGE_FLAG_BE 1 |
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#ifdef CONFIG_CPU_BIG_ENDIAN |
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#error conversion of header fields to LE not yet implemented |
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#else |
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#define __HEAD_FLAG_BE RISCV_IMAGE_FLAG_LE |
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#endif |
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#define __HEAD_FLAG(field) (__HEAD_FLAG_##field << \ |
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RISCV_IMAGE_FLAG_##field##_SHIFT) |
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#define __HEAD_FLAGS (__HEAD_FLAG(BE)) |
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#define RISCV_HEADER_VERSION_MAJOR 0 |
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#define RISCV_HEADER_VERSION_MINOR 2 |
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#define RISCV_HEADER_VERSION (RISCV_HEADER_VERSION_MAJOR << 16 | \ |
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RISCV_HEADER_VERSION_MINOR) |
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#ifndef __ASSEMBLY__ |
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/** |
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* struct riscv_image_header - riscv kernel image header |
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* @code0: Executable code |
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* @code1: Executable code |
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* @text_offset: Image load offset (little endian) |
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* @image_size: Effective Image size (little endian) |
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* @flags: kernel flags (little endian) |
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* @version: version |
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* @res1: reserved |
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* @res2: reserved |
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* @magic: Magic number (RISC-V specific; deprecated) |
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* @magic2: Magic number 2 (to match the ARM64 'magic' field pos) |
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* @res3: reserved (will be used for PE COFF offset) |
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* |
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* The intention is for this header format to be shared between multiple |
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* architectures to avoid a proliferation of image header formats. |
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*/ |
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struct riscv_image_header { |
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u32 code0; |
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u32 code1; |
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u64 text_offset; |
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u64 image_size; |
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u64 flags; |
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u32 version; |
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u32 res1; |
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u64 res2; |
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u64 magic; |
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u32 magic2; |
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u32 res3; |
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}; |
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#endif /* __ASSEMBLY__ */ |
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#endif /* _ASM_RISCV_IMAGE_H */
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