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205 lines
5.7 KiB
205 lines
5.7 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (C) 2012 Regents of the University of California |
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*/ |
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#ifndef _ASM_RISCV_BITOPS_H |
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#define _ASM_RISCV_BITOPS_H |
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#ifndef _LINUX_BITOPS_H |
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#error "Only <linux/bitops.h> can be included directly" |
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#endif /* _LINUX_BITOPS_H */ |
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#include <linux/compiler.h> |
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#include <linux/irqflags.h> |
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#include <asm/barrier.h> |
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#include <asm/bitsperlong.h> |
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#include <asm-generic/bitops/__ffs.h> |
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#include <asm-generic/bitops/ffz.h> |
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#include <asm-generic/bitops/fls.h> |
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#include <asm-generic/bitops/__fls.h> |
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#include <asm-generic/bitops/fls64.h> |
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#include <asm-generic/bitops/find.h> |
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#include <asm-generic/bitops/sched.h> |
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#include <asm-generic/bitops/ffs.h> |
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#include <asm-generic/bitops/hweight.h> |
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#if (BITS_PER_LONG == 64) |
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#define __AMO(op) "amo" #op ".d" |
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#elif (BITS_PER_LONG == 32) |
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#define __AMO(op) "amo" #op ".w" |
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#else |
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#error "Unexpected BITS_PER_LONG" |
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#endif |
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#define __test_and_op_bit_ord(op, mod, nr, addr, ord) \ |
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({ \ |
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unsigned long __res, __mask; \ |
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__mask = BIT_MASK(nr); \ |
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__asm__ __volatile__ ( \ |
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__AMO(op) #ord " %0, %2, %1" \ |
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: "=r" (__res), "+A" (addr[BIT_WORD(nr)]) \ |
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: "r" (mod(__mask)) \ |
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: "memory"); \ |
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((__res & __mask) != 0); \ |
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}) |
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#define __op_bit_ord(op, mod, nr, addr, ord) \ |
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__asm__ __volatile__ ( \ |
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__AMO(op) #ord " zero, %1, %0" \ |
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: "+A" (addr[BIT_WORD(nr)]) \ |
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: "r" (mod(BIT_MASK(nr))) \ |
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: "memory"); |
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#define __test_and_op_bit(op, mod, nr, addr) \ |
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__test_and_op_bit_ord(op, mod, nr, addr, .aqrl) |
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#define __op_bit(op, mod, nr, addr) \ |
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__op_bit_ord(op, mod, nr, addr, ) |
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/* Bitmask modifiers */ |
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#define __NOP(x) (x) |
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#define __NOT(x) (~(x)) |
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/** |
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* test_and_set_bit - Set a bit and return its old value |
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* @nr: Bit to set |
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* @addr: Address to count from |
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* |
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* This operation may be reordered on other architectures than x86. |
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*/ |
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static inline int test_and_set_bit(int nr, volatile unsigned long *addr) |
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{ |
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return __test_and_op_bit(or, __NOP, nr, addr); |
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} |
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/** |
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* test_and_clear_bit - Clear a bit and return its old value |
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* @nr: Bit to clear |
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* @addr: Address to count from |
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* |
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* This operation can be reordered on other architectures other than x86. |
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*/ |
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static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) |
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{ |
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return __test_and_op_bit(and, __NOT, nr, addr); |
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} |
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/** |
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* test_and_change_bit - Change a bit and return its old value |
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* @nr: Bit to change |
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* @addr: Address to count from |
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* |
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* This operation is atomic and cannot be reordered. |
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* It also implies a memory barrier. |
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*/ |
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static inline int test_and_change_bit(int nr, volatile unsigned long *addr) |
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{ |
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return __test_and_op_bit(xor, __NOP, nr, addr); |
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} |
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/** |
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* set_bit - Atomically set a bit in memory |
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* @nr: the bit to set |
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* @addr: the address to start counting from |
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* |
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* Note: there are no guarantees that this function will not be reordered |
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* on non x86 architectures, so if you are writing portable code, |
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* make sure not to rely on its reordering guarantees. |
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* |
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* Note that @nr may be almost arbitrarily large; this function is not |
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* restricted to acting on a single-word quantity. |
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*/ |
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static inline void set_bit(int nr, volatile unsigned long *addr) |
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{ |
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__op_bit(or, __NOP, nr, addr); |
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} |
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/** |
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* clear_bit - Clears a bit in memory |
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* @nr: Bit to clear |
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* @addr: Address to start counting from |
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* |
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* Note: there are no guarantees that this function will not be reordered |
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* on non x86 architectures, so if you are writing portable code, |
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* make sure not to rely on its reordering guarantees. |
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*/ |
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static inline void clear_bit(int nr, volatile unsigned long *addr) |
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{ |
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__op_bit(and, __NOT, nr, addr); |
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} |
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/** |
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* change_bit - Toggle a bit in memory |
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* @nr: Bit to change |
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* @addr: Address to start counting from |
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* |
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* change_bit() may be reordered on other architectures than x86. |
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* Note that @nr may be almost arbitrarily large; this function is not |
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* restricted to acting on a single-word quantity. |
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*/ |
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static inline void change_bit(int nr, volatile unsigned long *addr) |
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{ |
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__op_bit(xor, __NOP, nr, addr); |
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} |
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/** |
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* test_and_set_bit_lock - Set a bit and return its old value, for lock |
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* @nr: Bit to set |
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* @addr: Address to count from |
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* |
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* This operation is atomic and provides acquire barrier semantics. |
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* It can be used to implement bit locks. |
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*/ |
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static inline int test_and_set_bit_lock( |
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unsigned long nr, volatile unsigned long *addr) |
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{ |
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return __test_and_op_bit_ord(or, __NOP, nr, addr, .aq); |
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} |
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/** |
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* clear_bit_unlock - Clear a bit in memory, for unlock |
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* @nr: the bit to set |
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* @addr: the address to start counting from |
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* |
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* This operation is atomic and provides release barrier semantics. |
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*/ |
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static inline void clear_bit_unlock( |
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unsigned long nr, volatile unsigned long *addr) |
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{ |
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__op_bit_ord(and, __NOT, nr, addr, .rl); |
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} |
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/** |
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* __clear_bit_unlock - Clear a bit in memory, for unlock |
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* @nr: the bit to set |
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* @addr: the address to start counting from |
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* |
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* This operation is like clear_bit_unlock, however it is not atomic. |
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* It does provide release barrier semantics so it can be used to unlock |
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* a bit lock, however it would only be used if no other CPU can modify |
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* any bits in the memory until the lock is released (a good example is |
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* if the bit lock itself protects access to the other bits in the word). |
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* |
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* On RISC-V systems there seems to be no benefit to taking advantage of the |
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* non-atomic property here: it's a lot more instructions and we still have to |
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* provide release semantics anyway. |
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*/ |
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static inline void __clear_bit_unlock( |
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unsigned long nr, volatile unsigned long *addr) |
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{ |
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clear_bit_unlock(nr, addr); |
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} |
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#undef __test_and_op_bit |
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#undef __op_bit |
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#undef __NOP |
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#undef __NOT |
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#undef __AMO |
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#include <asm-generic/bitops/non-atomic.h> |
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#include <asm-generic/bitops/le.h> |
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#include <asm-generic/bitops/ext2-atomic.h> |
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#endif /* _ASM_RISCV_BITOPS_H */
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