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172 lines
4.3 KiB
172 lines
4.3 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* OpenRISC time.c |
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* |
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* Linux architectural port borrowing liberally from similar works of |
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* others. All original copyrights apply as per the original source |
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* declaration. |
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* |
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* Modifications for the OpenRISC architecture: |
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* Copyright (C) 2010-2011 Jonas Bonn <[email protected]> |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/time.h> |
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#include <linux/timex.h> |
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#include <linux/interrupt.h> |
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#include <linux/ftrace.h> |
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#include <linux/clocksource.h> |
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#include <linux/clockchips.h> |
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#include <linux/irq.h> |
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#include <linux/io.h> |
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#include <asm/cpuinfo.h> |
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/* Test the timer ticks to count, used in sync routine */ |
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inline void openrisc_timer_set(unsigned long count) |
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{ |
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mtspr(SPR_TTCR, count); |
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} |
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/* Set the timer to trigger in delta cycles */ |
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inline void openrisc_timer_set_next(unsigned long delta) |
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{ |
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u32 c; |
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/* Read 32-bit counter value, add delta, mask off the low 28 bits. |
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* We're guaranteed delta won't be bigger than 28 bits because the |
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* generic timekeeping code ensures that for us. |
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*/ |
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c = mfspr(SPR_TTCR); |
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c += delta; |
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c &= SPR_TTMR_TP; |
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/* Set counter and enable interrupt. |
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* Keep timer in continuous mode always. |
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*/ |
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mtspr(SPR_TTMR, SPR_TTMR_CR | SPR_TTMR_IE | c); |
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} |
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static int openrisc_timer_set_next_event(unsigned long delta, |
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struct clock_event_device *dev) |
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{ |
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openrisc_timer_set_next(delta); |
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return 0; |
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} |
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/* This is the clock event device based on the OR1K tick timer. |
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* As the timer is being used as a continuous clock-source (required for HR |
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* timers) we cannot enable the PERIODIC feature. The tick timer can run using |
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* one-shot events, so no problem. |
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*/ |
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DEFINE_PER_CPU(struct clock_event_device, clockevent_openrisc_timer); |
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void openrisc_clockevent_init(void) |
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{ |
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unsigned int cpu = smp_processor_id(); |
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struct clock_event_device *evt = |
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&per_cpu(clockevent_openrisc_timer, cpu); |
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struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu]; |
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mtspr(SPR_TTMR, SPR_TTMR_CR); |
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#ifdef CONFIG_SMP |
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evt->broadcast = tick_broadcast; |
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#endif |
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evt->name = "openrisc_timer_clockevent", |
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evt->features = CLOCK_EVT_FEAT_ONESHOT, |
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evt->rating = 300, |
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evt->set_next_event = openrisc_timer_set_next_event, |
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evt->cpumask = cpumask_of(cpu); |
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/* We only have 28 bits */ |
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clockevents_config_and_register(evt, cpuinfo->clock_frequency, |
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100, 0x0fffffff); |
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} |
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static inline void timer_ack(void) |
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{ |
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/* Clear the IP bit and disable further interrupts */ |
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/* This can be done very simply... we just need to keep the timer |
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running, so just maintain the CR bits while clearing the rest |
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of the register |
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*/ |
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mtspr(SPR_TTMR, SPR_TTMR_CR); |
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} |
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/* |
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* The timer interrupt is mostly handled in generic code nowadays... this |
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* function just acknowledges the interrupt and fires the event handler that |
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* has been set on the clockevent device by the generic time management code. |
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* |
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* This function needs to be called by the timer exception handler and that's |
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* all the exception handler needs to do. |
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*/ |
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irqreturn_t __irq_entry timer_interrupt(struct pt_regs *regs) |
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{ |
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struct pt_regs *old_regs = set_irq_regs(regs); |
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unsigned int cpu = smp_processor_id(); |
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struct clock_event_device *evt = |
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&per_cpu(clockevent_openrisc_timer, cpu); |
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timer_ack(); |
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/* |
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* update_process_times() expects us to have called irq_enter(). |
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*/ |
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irq_enter(); |
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evt->event_handler(evt); |
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irq_exit(); |
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set_irq_regs(old_regs); |
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return IRQ_HANDLED; |
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} |
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/** |
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* Clocksource: Based on OpenRISC timer/counter |
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* |
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* This sets up the OpenRISC Tick Timer as a clock source. The tick timer |
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* is 32 bits wide and runs at the CPU clock frequency. |
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*/ |
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static u64 openrisc_timer_read(struct clocksource *cs) |
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{ |
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return (u64) mfspr(SPR_TTCR); |
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} |
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static struct clocksource openrisc_timer = { |
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.name = "openrisc_timer", |
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.rating = 200, |
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.read = openrisc_timer_read, |
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.mask = CLOCKSOURCE_MASK(32), |
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.flags = CLOCK_SOURCE_IS_CONTINUOUS, |
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}; |
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static int __init openrisc_timer_init(void) |
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{ |
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struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()]; |
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if (clocksource_register_hz(&openrisc_timer, cpuinfo->clock_frequency)) |
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panic("failed to register clocksource"); |
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/* Enable the incrementer: 'continuous' mode with interrupt disabled */ |
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mtspr(SPR_TTMR, SPR_TTMR_CR); |
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return 0; |
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} |
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void __init time_init(void) |
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{ |
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u32 upr; |
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upr = mfspr(SPR_UPR); |
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if (!(upr & SPR_UPR_TTP)) |
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panic("Linux not supported on devices without tick timer"); |
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openrisc_timer_init(); |
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openrisc_clockevent_init(); |
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}
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