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118 lines
2.6 KiB
118 lines
2.6 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Purna Chandra Mandal, [email protected] |
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* Copyright (C) 2015 Microchip Technology Inc. All rights reserved. |
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*/ |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/of_platform.h> |
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#include <asm/mach-pic32/pic32.h> |
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#include "pic32mzda.h" |
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#define PIC32_CFGCON 0x0000 |
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#define PIC32_DEVID 0x0020 |
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#define PIC32_SYSKEY 0x0030 |
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#define PIC32_CFGEBIA 0x00c0 |
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#define PIC32_CFGEBIC 0x00d0 |
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#define PIC32_CFGCON2 0x00f0 |
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#define PIC32_RCON 0x1240 |
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static void __iomem *pic32_conf_base; |
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static DEFINE_SPINLOCK(config_lock); |
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static u32 pic32_reset_status; |
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static u32 pic32_conf_get_reg_field(u32 offset, u32 rshift, u32 mask) |
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{ |
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u32 v; |
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v = readl(pic32_conf_base + offset); |
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v >>= rshift; |
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v &= mask; |
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return v; |
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} |
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static u32 pic32_conf_modify_atomic(u32 offset, u32 mask, u32 set) |
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{ |
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u32 v; |
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unsigned long flags; |
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spin_lock_irqsave(&config_lock, flags); |
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v = readl(pic32_conf_base + offset); |
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v &= ~mask; |
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v |= (set & mask); |
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writel(v, pic32_conf_base + offset); |
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spin_unlock_irqrestore(&config_lock, flags); |
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return 0; |
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} |
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int pic32_enable_lcd(void) |
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{ |
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return pic32_conf_modify_atomic(PIC32_CFGCON2, BIT(31), BIT(31)); |
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} |
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int pic32_disable_lcd(void) |
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{ |
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return pic32_conf_modify_atomic(PIC32_CFGCON2, BIT(31), 0); |
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} |
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int pic32_set_lcd_mode(int mode) |
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{ |
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u32 mask = mode ? BIT(30) : 0; |
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return pic32_conf_modify_atomic(PIC32_CFGCON2, BIT(30), mask); |
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} |
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int pic32_set_sdhci_adma_fifo_threshold(u32 rthrsh, u32 wthrsh) |
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{ |
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u32 clr, set; |
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clr = (0x3ff << 4) | (0x3ff << 16); |
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set = (rthrsh << 4) | (wthrsh << 16); |
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return pic32_conf_modify_atomic(PIC32_CFGCON2, clr, set); |
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} |
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void pic32_syskey_unlock_debug(const char *func, const ulong line) |
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{ |
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void __iomem *syskey = pic32_conf_base + PIC32_SYSKEY; |
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pr_debug("%s: called from %s:%lu\n", __func__, func, line); |
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writel(0x00000000, syskey); |
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writel(0xAA996655, syskey); |
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writel(0x556699AA, syskey); |
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} |
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static u32 pic32_get_device_id(void) |
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{ |
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return pic32_conf_get_reg_field(PIC32_DEVID, 0, 0x0fffffff); |
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} |
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static u32 pic32_get_device_version(void) |
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{ |
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return pic32_conf_get_reg_field(PIC32_DEVID, 28, 0xf); |
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} |
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u32 pic32_get_boot_status(void) |
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{ |
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return pic32_reset_status; |
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} |
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EXPORT_SYMBOL(pic32_get_boot_status); |
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void __init pic32_config_init(void) |
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{ |
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pic32_conf_base = ioremap(PIC32_BASE_CONFIG, 0x110); |
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if (!pic32_conf_base) |
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panic("pic32: config base not mapped"); |
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/* Boot Status */ |
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pic32_reset_status = readl(pic32_conf_base + PIC32_RCON); |
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writel(-1, PIC32_CLR(pic32_conf_base + PIC32_RCON)); |
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/* Device Inforation */ |
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pr_info("Device Id: 0x%08x, Device Ver: 0x%04x\n", |
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pic32_get_device_id(), |
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pic32_get_device_version()); |
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}
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