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291 lines
7.3 KiB
291 lines
7.3 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Ralink RT288x SoC PCI register definitions |
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* |
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* Copyright (C) 2009 John Crispin <[email protected]> |
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* Copyright (C) 2009 Gabor Juhos <[email protected]> |
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* |
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* Parts of this file are based on Ralink's 2.6.21 BSP |
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*/ |
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#include <linux/delay.h> |
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#include <linux/types.h> |
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#include <linux/pci.h> |
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#include <linux/io.h> |
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#include <linux/init.h> |
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#include <linux/of_platform.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_pci.h> |
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#include <asm/mach-ralink/rt288x.h> |
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#define RT2880_PCI_BASE 0x00440000 |
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#define RT288X_CPU_IRQ_PCI 4 |
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#define RT2880_PCI_MEM_BASE 0x20000000 |
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#define RT2880_PCI_MEM_SIZE 0x10000000 |
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#define RT2880_PCI_IO_BASE 0x00460000 |
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#define RT2880_PCI_IO_SIZE 0x00010000 |
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#define RT2880_PCI_REG_PCICFG_ADDR 0x00 |
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#define RT2880_PCI_REG_PCIMSK_ADDR 0x0c |
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#define RT2880_PCI_REG_BAR0SETUP_ADDR 0x10 |
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#define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18 |
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#define RT2880_PCI_REG_CONFIG_ADDR 0x20 |
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#define RT2880_PCI_REG_CONFIG_DATA 0x24 |
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#define RT2880_PCI_REG_MEMBASE 0x28 |
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#define RT2880_PCI_REG_IOBASE 0x2c |
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#define RT2880_PCI_REG_ID 0x30 |
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#define RT2880_PCI_REG_CLASS 0x34 |
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#define RT2880_PCI_REG_SUBID 0x38 |
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#define RT2880_PCI_REG_ARBCTL 0x80 |
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static void __iomem *rt2880_pci_base; |
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static DEFINE_SPINLOCK(rt2880_pci_lock); |
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static u32 rt2880_pci_reg_read(u32 reg) |
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{ |
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return readl(rt2880_pci_base + reg); |
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} |
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static void rt2880_pci_reg_write(u32 val, u32 reg) |
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{ |
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writel(val, rt2880_pci_base + reg); |
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} |
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static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot, |
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unsigned int func, unsigned int where) |
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{ |
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return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | |
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0x80000000); |
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} |
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static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 *val) |
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{ |
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unsigned long flags; |
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u32 address; |
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u32 data; |
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address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), |
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PCI_FUNC(devfn), where); |
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spin_lock_irqsave(&rt2880_pci_lock, flags); |
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rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); |
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data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA); |
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spin_unlock_irqrestore(&rt2880_pci_lock, flags); |
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switch (size) { |
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case 1: |
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*val = (data >> ((where & 3) << 3)) & 0xff; |
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break; |
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case 2: |
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*val = (data >> ((where & 3) << 3)) & 0xffff; |
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break; |
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case 4: |
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*val = data; |
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break; |
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} |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 val) |
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{ |
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unsigned long flags; |
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u32 address; |
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u32 data; |
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address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), |
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PCI_FUNC(devfn), where); |
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spin_lock_irqsave(&rt2880_pci_lock, flags); |
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rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); |
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data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA); |
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switch (size) { |
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case 1: |
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data = (data & ~(0xff << ((where & 3) << 3))) | |
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(val << ((where & 3) << 3)); |
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break; |
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case 2: |
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data = (data & ~(0xffff << ((where & 3) << 3))) | |
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(val << ((where & 3) << 3)); |
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break; |
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case 4: |
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data = val; |
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break; |
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} |
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rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA); |
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spin_unlock_irqrestore(&rt2880_pci_lock, flags); |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static struct pci_ops rt2880_pci_ops = { |
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.read = rt2880_pci_config_read, |
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.write = rt2880_pci_config_write, |
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}; |
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static struct resource rt2880_pci_mem_resource = { |
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.name = "PCI MEM space", |
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.start = RT2880_PCI_MEM_BASE, |
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.end = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1, |
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.flags = IORESOURCE_MEM, |
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}; |
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static struct resource rt2880_pci_io_resource = { |
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.name = "PCI IO space", |
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.start = RT2880_PCI_IO_BASE, |
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.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1, |
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.flags = IORESOURCE_IO, |
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}; |
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static struct pci_controller rt2880_pci_controller = { |
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.pci_ops = &rt2880_pci_ops, |
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.mem_resource = &rt2880_pci_mem_resource, |
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.io_resource = &rt2880_pci_io_resource, |
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}; |
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static inline u32 rt2880_pci_read_u32(unsigned long reg) |
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{ |
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unsigned long flags; |
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u32 address; |
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u32 ret; |
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address = rt2880_pci_get_cfgaddr(0, 0, 0, reg); |
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spin_lock_irqsave(&rt2880_pci_lock, flags); |
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rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); |
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ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA); |
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spin_unlock_irqrestore(&rt2880_pci_lock, flags); |
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return ret; |
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} |
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static inline void rt2880_pci_write_u32(unsigned long reg, u32 val) |
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{ |
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unsigned long flags; |
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u32 address; |
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address = rt2880_pci_get_cfgaddr(0, 0, 0, reg); |
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spin_lock_irqsave(&rt2880_pci_lock, flags); |
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rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); |
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rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA); |
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spin_unlock_irqrestore(&rt2880_pci_lock, flags); |
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} |
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int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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int irq = -1; |
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if (dev->bus->number != 0) |
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return irq; |
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switch (PCI_SLOT(dev->devfn)) { |
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case 0x00: |
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break; |
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case 0x11: |
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irq = RT288X_CPU_IRQ_PCI; |
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break; |
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default: |
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pr_err("%s:%s[%d] trying to alloc unknown pci irq\n", |
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__FILE__, __func__, __LINE__); |
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BUG(); |
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break; |
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} |
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return irq; |
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} |
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static int rt288x_pci_probe(struct platform_device *pdev) |
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{ |
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void __iomem *io_map_base; |
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rt2880_pci_base = ioremap(RT2880_PCI_BASE, PAGE_SIZE); |
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io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE); |
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rt2880_pci_controller.io_map_base = (unsigned long) io_map_base; |
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set_io_port_base((unsigned long) io_map_base); |
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ioport_resource.start = RT2880_PCI_IO_BASE; |
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ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1; |
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rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR); |
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udelay(1); |
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rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL); |
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rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR); |
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rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE); |
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rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE); |
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rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR); |
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rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID); |
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rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS); |
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rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID); |
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rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR); |
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rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000); |
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(void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0); |
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rt2880_pci_controller.of_node = pdev->dev.of_node; |
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register_pci_controller(&rt2880_pci_controller); |
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return 0; |
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} |
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int pcibios_plat_dev_init(struct pci_dev *dev) |
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{ |
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static bool slot0_init; |
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/* |
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* Nobody seems to initialize slot 0, but this platform requires it, so |
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* do it once when some other slot is being enabled. The PCI subsystem |
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* should configure other slots properly, so no need to do anything |
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* special for those. |
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*/ |
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if (!slot0_init && dev->bus->number == 0) { |
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u16 cmd; |
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u32 bar0; |
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slot0_init = true; |
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pci_bus_write_config_dword(dev->bus, 0, PCI_BASE_ADDRESS_0, |
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0x08000000); |
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pci_bus_read_config_dword(dev->bus, 0, PCI_BASE_ADDRESS_0, |
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&bar0); |
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pci_bus_read_config_word(dev->bus, 0, PCI_COMMAND, &cmd); |
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cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; |
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pci_bus_write_config_word(dev->bus, 0, PCI_COMMAND, cmd); |
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} |
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return 0; |
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} |
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static const struct of_device_id rt288x_pci_match[] = { |
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{ .compatible = "ralink,rt288x-pci" }, |
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{}, |
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}; |
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static struct platform_driver rt288x_pci_driver = { |
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.probe = rt288x_pci_probe, |
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.driver = { |
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.name = "rt288x-pci", |
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.of_match_table = rt288x_pci_match, |
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}, |
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}; |
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int __init pcibios_init(void) |
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{ |
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int ret = platform_driver_register(&rt288x_pci_driver); |
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if (ret) |
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pr_info("rt288x-pci: Error registering platform driver!"); |
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return ret; |
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} |
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arch_initcall(pcibios_init);
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