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231 lines
7.1 KiB
231 lines
7.1 KiB
/* |
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* Copyright 2001 MontaVista Software Inc. |
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* Author: MontaVista Software, Inc. |
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* [email protected] |
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* |
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* Copyright (C) 2000-2001 Toshiba Corporation |
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* Copyright (C) 2004 by Ralf Baechle ([email protected]) |
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* |
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* Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c |
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* |
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* Define the pci_ops for TX3927. |
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* |
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* Much of the code is derived from the original DDB5074 port by |
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* Geert Uytterhoeven <[email protected]> |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License as published by the |
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* Free Software Foundation; either version 2 of the License, or (at your |
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* option) any later version. |
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* |
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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* You should have received a copy of the GNU General Public License along |
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* with this program; if not, write to the Free Software Foundation, Inc., |
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* 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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#include <linux/types.h> |
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#include <linux/pci.h> |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <asm/addrspace.h> |
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#include <asm/txx9irq.h> |
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#include <asm/txx9/pci.h> |
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#include <asm/txx9/tx3927.h> |
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static int mkaddr(struct pci_bus *bus, unsigned char devfn, unsigned char where) |
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{ |
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if (bus->parent == NULL && |
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devfn >= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU, 0)) |
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return -1; |
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tx3927_pcicptr->ica = |
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((bus->number & 0xff) << 0x10) | |
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((devfn & 0xff) << 0x08) | |
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(where & 0xfc) | (bus->parent ? 1 : 0); |
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/* clear M_ABORT and Disable M_ABORT Int. */ |
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tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT; |
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tx3927_pcicptr->pcistatim &= ~PCI_STATUS_REC_MASTER_ABORT; |
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return 0; |
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} |
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static inline int check_abort(void) |
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{ |
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if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT) { |
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tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT; |
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tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT; |
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/* flush write buffer */ |
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iob(); |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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} |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int tx3927_pci_read_config(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 * val) |
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{ |
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if (mkaddr(bus, devfn, where)) { |
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*val = 0xffffffff; |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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} |
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switch (size) { |
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case 1: |
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*val = *(volatile u8 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3)); |
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break; |
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case 2: |
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*val = le16_to_cpu(*(volatile u16 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3))); |
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break; |
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case 4: |
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*val = le32_to_cpu(tx3927_pcicptr->icd); |
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break; |
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} |
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return check_abort(); |
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} |
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static int tx3927_pci_write_config(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 val) |
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{ |
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if (mkaddr(bus, devfn, where)) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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switch (size) { |
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case 1: |
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*(volatile u8 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3)) = val; |
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break; |
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case 2: |
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*(volatile u16 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 2)) = |
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cpu_to_le16(val); |
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break; |
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case 4: |
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tx3927_pcicptr->icd = cpu_to_le32(val); |
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} |
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return check_abort(); |
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} |
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static struct pci_ops tx3927_pci_ops = { |
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.read = tx3927_pci_read_config, |
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.write = tx3927_pci_write_config, |
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}; |
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void __init tx3927_pcic_setup(struct pci_controller *channel, |
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unsigned long sdram_size, int extarb) |
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{ |
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unsigned long flags; |
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unsigned long io_base = |
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channel->io_resource->start + mips_io_port_base - IO_BASE; |
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unsigned long io_size = |
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channel->io_resource->end - channel->io_resource->start; |
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unsigned long io_pciaddr = |
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channel->io_resource->start - channel->io_offset; |
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unsigned long mem_base = |
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channel->mem_resource->start; |
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unsigned long mem_size = |
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channel->mem_resource->end - channel->mem_resource->start; |
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unsigned long mem_pciaddr = |
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channel->mem_resource->start - channel->mem_offset; |
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printk(KERN_INFO "TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s", |
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tx3927_pcicptr->did, tx3927_pcicptr->vid, |
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tx3927_pcicptr->rid, |
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extarb ? "External" : "Internal"); |
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channel->pci_ops = &tx3927_pci_ops; |
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local_irq_save(flags); |
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/* Disable External PCI Config. Access */ |
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tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD; |
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#ifdef __BIG_ENDIAN |
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tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE | |
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TX3927_PCIC_LBC_TIBSE | |
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TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE; |
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#endif |
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/* LB->PCI mappings */ |
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tx3927_pcicptr->iomas = ~(io_size - 1); |
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tx3927_pcicptr->ilbioma = io_base; |
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tx3927_pcicptr->ipbioma = io_pciaddr; |
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tx3927_pcicptr->mmas = ~(mem_size - 1); |
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tx3927_pcicptr->ilbmma = mem_base; |
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tx3927_pcicptr->ipbmma = mem_pciaddr; |
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/* PCI->LB mappings */ |
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tx3927_pcicptr->iobas = 0xffffffff; |
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tx3927_pcicptr->ioba = 0; |
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tx3927_pcicptr->tlbioma = 0; |
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tx3927_pcicptr->mbas = ~(sdram_size - 1); |
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tx3927_pcicptr->mba = 0; |
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tx3927_pcicptr->tlbmma = 0; |
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/* Enable Direct mapping Address Space Decoder */ |
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tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; |
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/* Clear All Local Bus Status */ |
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tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; |
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/* Enable All Local Bus Interrupts */ |
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tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL; |
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/* Clear All PCI Status Error */ |
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tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL; |
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/* Enable All PCI Status Error Interrupts */ |
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tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL; |
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/* PCIC Int => IRC IRQ10 */ |
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tx3927_pcicptr->il = TX3927_IR_PCI; |
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/* Target Control (per errata) */ |
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tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; |
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/* Enable Bus Arbiter */ |
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if (!extarb) |
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tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; |
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tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | |
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PCI_COMMAND_MEMORY | |
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PCI_COMMAND_IO | |
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PCI_COMMAND_PARITY | PCI_COMMAND_SERR; |
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local_irq_restore(flags); |
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} |
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static irqreturn_t tx3927_pcierr_interrupt(int irq, void *dev_id) |
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{ |
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struct pt_regs *regs = get_irq_regs(); |
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if (txx9_pci_err_action != TXX9_PCI_ERR_IGNORE) { |
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printk(KERN_WARNING "PCI error interrupt at 0x%08lx.\n", |
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regs->cp0_epc); |
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printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n", |
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tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat); |
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} |
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if (txx9_pci_err_action != TXX9_PCI_ERR_PANIC) { |
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/* clear all pci errors */ |
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tx3927_pcicptr->pcistat |= TX3927_PCIC_PCISTATIM_ALL; |
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tx3927_pcicptr->istat = TX3927_PCIC_IIM_ALL; |
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tx3927_pcicptr->tstat = TX3927_PCIC_TIM_ALL; |
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tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; |
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return IRQ_HANDLED; |
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} |
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console_verbose(); |
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panic("PCI error."); |
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} |
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void __init tx3927_setup_pcierr_irq(void) |
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{ |
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if (request_irq(TXX9_IRQ_BASE + TX3927_IR_PCI, |
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tx3927_pcierr_interrupt, |
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0, "PCI error", |
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(void *)TX3927_PCIC_REG)) |
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printk(KERN_WARNING "Failed to request irq for PCIERR\n"); |
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}
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