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297 lines
7.6 KiB
297 lines
7.6 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* PROM library initialisation code. |
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* |
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* Copyright (C) 1999,2000,2004,2005,2012 MIPS Technologies, Inc. |
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* All rights reserved. |
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* Authors: Carsten Langgaard <[email protected]> |
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* Maciej W. Rozycki <[email protected]> |
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* Steven J. Hill <[email protected]> |
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*/ |
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#include <linux/init.h> |
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#include <linux/string.h> |
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#include <linux/kernel.h> |
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#include <linux/pci_regs.h> |
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#include <linux/serial_core.h> |
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#include <asm/cacheflush.h> |
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#include <asm/smp-ops.h> |
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#include <asm/traps.h> |
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#include <asm/fw/fw.h> |
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#include <asm/mips-cps.h> |
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#include <asm/mips-boards/generic.h> |
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#include <asm/mips-boards/malta.h> |
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static int mips_revision_corid; |
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int mips_revision_sconid; |
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/* Bonito64 system controller register base. */ |
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unsigned long _pcictrl_bonito; |
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unsigned long _pcictrl_bonito_pcicfg; |
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/* GT64120 system controller register base */ |
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unsigned long _pcictrl_gt64120; |
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/* MIPS System controller register base */ |
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unsigned long _pcictrl_msc; |
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#ifdef CONFIG_SERIAL_8250_CONSOLE |
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static void __init console_config(void) |
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{ |
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char console_string[40]; |
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int baud = 0; |
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char parity = '\0', bits = '\0', flow = '\0'; |
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char *s; |
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s = fw_getenv("modetty0"); |
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if (s) { |
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while (*s >= '0' && *s <= '9') |
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baud = baud*10 + *s++ - '0'; |
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if (*s == ',') |
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s++; |
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if (*s) |
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parity = *s++; |
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if (*s == ',') |
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s++; |
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if (*s) |
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bits = *s++; |
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if (*s == ',') |
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s++; |
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if (*s == 'h') |
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flow = 'r'; |
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} |
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if (baud == 0) |
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baud = 38400; |
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if (parity != 'n' && parity != 'o' && parity != 'e') |
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parity = 'n'; |
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if (bits != '7' && bits != '8') |
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bits = '8'; |
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if (flow == '\0') |
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flow = 'r'; |
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if ((strstr(fw_getcmdline(), "earlycon=")) == NULL) { |
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sprintf(console_string, "uart8250,io,0x3f8,%d%c%c", baud, |
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parity, bits); |
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setup_earlycon(console_string); |
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} |
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if ((strstr(fw_getcmdline(), "console=")) == NULL) { |
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sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, |
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parity, bits, flow); |
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strcat(fw_getcmdline(), console_string); |
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pr_info("Config serial console:%s\n", console_string); |
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} |
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} |
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#endif |
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static void __init mips_nmi_setup(void) |
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{ |
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void *base; |
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base = cpu_has_veic ? |
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(void *)(CAC_BASE + 0xa80) : |
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(void *)(CAC_BASE + 0x380); |
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memcpy(base, except_vec_nmi, 0x80); |
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flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); |
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} |
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static void __init mips_ejtag_setup(void) |
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{ |
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void *base; |
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extern char except_vec_ejtag_debug[]; |
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base = cpu_has_veic ? |
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(void *)(CAC_BASE + 0xa00) : |
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(void *)(CAC_BASE + 0x300); |
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memcpy(base, except_vec_ejtag_debug, 0x80); |
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flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); |
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} |
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phys_addr_t mips_cpc_default_phys_base(void) |
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{ |
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return CPC_BASE_ADDR; |
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} |
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void __init prom_init(void) |
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{ |
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/* |
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* early setup of _pcictrl_bonito so that we can determine |
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* the system controller on a CORE_EMUL board |
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*/ |
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_pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE); |
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mips_revision_corid = MIPS_REVISION_CORID; |
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if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { |
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if (BONITO_PCIDID == 0x0001df53 || |
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BONITO_PCIDID == 0x0003df53) |
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mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; |
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else |
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mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; |
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} |
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mips_revision_sconid = MIPS_REVISION_SCONID; |
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if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) { |
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switch (mips_revision_corid) { |
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case MIPS_REVISION_CORID_QED_RM5261: |
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case MIPS_REVISION_CORID_CORE_LV: |
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case MIPS_REVISION_CORID_CORE_FPGA: |
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case MIPS_REVISION_CORID_CORE_FPGAR2: |
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mips_revision_sconid = MIPS_REVISION_SCON_GT64120; |
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break; |
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case MIPS_REVISION_CORID_CORE_EMUL_BON: |
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case MIPS_REVISION_CORID_BONITO64: |
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case MIPS_REVISION_CORID_CORE_20K: |
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mips_revision_sconid = MIPS_REVISION_SCON_BONITO; |
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break; |
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case MIPS_REVISION_CORID_CORE_MSC: |
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case MIPS_REVISION_CORID_CORE_FPGA2: |
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case MIPS_REVISION_CORID_CORE_24K: |
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/* |
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* SOCit/ROCit support is essentially identical |
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* but make an attempt to distinguish them |
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*/ |
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mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; |
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break; |
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case MIPS_REVISION_CORID_CORE_FPGA3: |
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case MIPS_REVISION_CORID_CORE_FPGA4: |
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case MIPS_REVISION_CORID_CORE_FPGA5: |
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case MIPS_REVISION_CORID_CORE_EMUL_MSC: |
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default: |
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/* See above */ |
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mips_revision_sconid = MIPS_REVISION_SCON_ROCIT; |
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break; |
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} |
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} |
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switch (mips_revision_sconid) { |
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u32 start, map, mask, data; |
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case MIPS_REVISION_SCON_GT64120: |
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/* |
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* Setup the North bridge to do Master byte-lane swapping |
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* when running in bigendian. |
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*/ |
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_pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000); |
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#ifdef CONFIG_CPU_LITTLE_ENDIAN |
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GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | |
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GT_PCI0_CMD_SBYTESWAP_BIT); |
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#else |
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GT_WRITE(GT_PCI0_CMD_OFS, 0); |
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#endif |
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/* Fix up PCI I/O mapping if necessary (for Atlas). */ |
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start = GT_READ(GT_PCI0IOLD_OFS); |
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map = GT_READ(GT_PCI0IOREMAP_OFS); |
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if ((start & map) != 0) { |
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map &= ~start; |
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GT_WRITE(GT_PCI0IOREMAP_OFS, map); |
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} |
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set_io_port_base(MALTA_GT_PORT_BASE); |
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break; |
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case MIPS_REVISION_SCON_BONITO: |
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_pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); |
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/* |
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* Disable Bonito IOBC. |
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*/ |
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BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & |
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~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | |
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BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); |
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/* |
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* Setup the North bridge to do Master byte-lane swapping |
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* when running in bigendian. |
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*/ |
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#ifdef CONFIG_CPU_LITTLE_ENDIAN |
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BONITO_BONGENCFG = BONITO_BONGENCFG & |
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~(BONITO_BONGENCFG_MSTRBYTESWAP | |
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BONITO_BONGENCFG_BYTESWAP); |
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#else |
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BONITO_BONGENCFG = BONITO_BONGENCFG | |
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BONITO_BONGENCFG_MSTRBYTESWAP | |
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BONITO_BONGENCFG_BYTESWAP; |
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#endif |
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set_io_port_base(MALTA_BONITO_PORT_BASE); |
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break; |
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case MIPS_REVISION_SCON_SOCIT: |
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case MIPS_REVISION_SCON_ROCIT: |
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_pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); |
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mips_pci_controller: |
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mb(); |
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MSC_READ(MSC01_PCI_CFG, data); |
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MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); |
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wmb(); |
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/* Fix up lane swapping. */ |
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#ifdef CONFIG_CPU_LITTLE_ENDIAN |
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MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); |
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#else |
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MSC_WRITE(MSC01_PCI_SWAP, |
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MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | |
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MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | |
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MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); |
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#endif |
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/* |
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* Setup the Malta max (2GB) memory for PCI DMA in host bridge |
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* in transparent addressing mode. |
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*/ |
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mask = PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_PREFETCH; |
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MSC_WRITE(MSC01_PCI_BAR0, mask); |
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MSC_WRITE(MSC01_PCI_HEAD4, mask); |
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mask &= MSC01_PCI_BAR0_SIZE_MSK; |
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MSC_WRITE(MSC01_PCI_P2SCMSKL, mask); |
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MSC_WRITE(MSC01_PCI_P2SCMAPL, mask); |
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/* Don't handle target retries indefinitely. */ |
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if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == |
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MSC01_PCI_CFG_MAXRTRY_MSK) |
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data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK << |
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MSC01_PCI_CFG_MAXRTRY_SHF)) | |
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((MSC01_PCI_CFG_MAXRTRY_MSK - 1) << |
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MSC01_PCI_CFG_MAXRTRY_SHF); |
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wmb(); |
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MSC_WRITE(MSC01_PCI_CFG, data); |
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mb(); |
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set_io_port_base(MALTA_MSC_PORT_BASE); |
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break; |
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case MIPS_REVISION_SCON_SOCITSC: |
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case MIPS_REVISION_SCON_SOCITSCP: |
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_pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000); |
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goto mips_pci_controller; |
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default: |
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/* Unknown system controller */ |
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while (1); /* We die here... */ |
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} |
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board_nmi_handler_setup = mips_nmi_setup; |
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board_ejtag_handler_setup = mips_ejtag_setup; |
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fw_init_cmdline(); |
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fw_meminit(); |
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#ifdef CONFIG_SERIAL_8250_CONSOLE |
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console_config(); |
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#endif |
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/* Early detection of CMP support */ |
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mips_cpc_probe(); |
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if (!register_cps_smp_ops()) |
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return; |
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if (!register_cmp_smp_ops()) |
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return; |
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if (!register_vsmp_smp_ops()) |
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return; |
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register_up_smp_ops(); |
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}
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