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366 lines
11 KiB
366 lines
11 KiB
/* |
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights |
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* reserved. |
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* |
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* This software is available to you under a choice of one of two |
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* licenses. You may choose to be licensed under the terms of the GNU |
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* General Public License (GPL) Version 2, available from the file |
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* COPYING in the main directory of this source tree, or the NetLogic |
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* license below: |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* |
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR |
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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#ifndef _NLM_HAL_PIC_H |
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#define _NLM_HAL_PIC_H |
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/* PIC Specific registers */ |
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#define PIC_CTRL 0x00 |
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/* PIC control register defines */ |
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#define PIC_CTRL_ITV 32 /* interrupt timeout value */ |
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#define PIC_CTRL_ICI 19 /* ICI interrupt timeout enable */ |
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#define PIC_CTRL_ITE 18 /* interrupt timeout enable */ |
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#define PIC_CTRL_STE 10 /* system timer interrupt enable */ |
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#define PIC_CTRL_WWR1 8 /* watchdog 1 wraparound count for reset */ |
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#define PIC_CTRL_WWR0 6 /* watchdog 0 wraparound count for reset */ |
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#define PIC_CTRL_WWN1 4 /* watchdog 1 wraparound count for NMI */ |
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#define PIC_CTRL_WWN0 2 /* watchdog 0 wraparound count for NMI */ |
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#define PIC_CTRL_WTE 0 /* watchdog timer enable */ |
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/* PIC Status register defines */ |
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#define PIC_ICI_STATUS 33 /* ICI interrupt timeout status */ |
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#define PIC_ITE_STATUS 32 /* interrupt timeout status */ |
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#define PIC_STS_STATUS 4 /* System timer interrupt status */ |
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#define PIC_WNS_STATUS 2 /* NMI status for watchdog timers */ |
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#define PIC_WIS_STATUS 0 /* Interrupt status for watchdog timers */ |
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/* PIC IPI control register offsets */ |
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#define PIC_IPICTRL_NMI 32 |
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#define PIC_IPICTRL_RIV 20 /* received interrupt vector */ |
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#define PIC_IPICTRL_IDB 16 /* interrupt destination base */ |
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#define PIC_IPICTRL_DTE 0 /* interrupt destination thread enables */ |
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/* PIC IRT register offsets */ |
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#define PIC_IRT_ENABLE 31 |
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#define PIC_IRT_NMI 29 |
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#define PIC_IRT_SCH 28 /* Scheduling scheme */ |
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#define PIC_IRT_RVEC 20 /* Interrupt receive vectors */ |
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#define PIC_IRT_DT 19 /* Destination type */ |
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#define PIC_IRT_DB 16 /* Destination base */ |
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#define PIC_IRT_DTE 0 /* Destination thread enables */ |
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#define PIC_BYTESWAP 0x02 |
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#define PIC_STATUS 0x04 |
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#define PIC_INTR_TIMEOUT 0x06 |
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#define PIC_ICI0_INTR_TIMEOUT 0x08 |
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#define PIC_ICI1_INTR_TIMEOUT 0x0a |
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#define PIC_ICI2_INTR_TIMEOUT 0x0c |
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#define PIC_IPI_CTL 0x0e |
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#define PIC_INT_ACK 0x10 |
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#define PIC_INT_PENDING0 0x12 |
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#define PIC_INT_PENDING1 0x14 |
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#define PIC_INT_PENDING2 0x16 |
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#define PIC_WDOG0_MAXVAL 0x18 |
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#define PIC_WDOG0_COUNT 0x1a |
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#define PIC_WDOG0_ENABLE0 0x1c |
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#define PIC_WDOG0_ENABLE1 0x1e |
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#define PIC_WDOG0_BEATCMD 0x20 |
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#define PIC_WDOG0_BEAT0 0x22 |
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#define PIC_WDOG0_BEAT1 0x24 |
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#define PIC_WDOG1_MAXVAL 0x26 |
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#define PIC_WDOG1_COUNT 0x28 |
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#define PIC_WDOG1_ENABLE0 0x2a |
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#define PIC_WDOG1_ENABLE1 0x2c |
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#define PIC_WDOG1_BEATCMD 0x2e |
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#define PIC_WDOG1_BEAT0 0x30 |
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#define PIC_WDOG1_BEAT1 0x32 |
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#define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0)) |
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#define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0)) |
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#define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0)) |
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#define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0)) |
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#define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0)) |
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#define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0)) |
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#define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0)) |
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#define PIC_TIMER0_MAXVAL 0x34 |
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#define PIC_TIMER1_MAXVAL 0x36 |
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#define PIC_TIMER2_MAXVAL 0x38 |
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#define PIC_TIMER3_MAXVAL 0x3a |
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#define PIC_TIMER4_MAXVAL 0x3c |
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#define PIC_TIMER5_MAXVAL 0x3e |
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#define PIC_TIMER6_MAXVAL 0x40 |
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#define PIC_TIMER7_MAXVAL 0x42 |
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#define PIC_TIMER_MAXVAL(i) (PIC_TIMER0_MAXVAL + ((i) * 2)) |
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#define PIC_TIMER0_COUNT 0x44 |
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#define PIC_TIMER1_COUNT 0x46 |
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#define PIC_TIMER2_COUNT 0x48 |
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#define PIC_TIMER3_COUNT 0x4a |
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#define PIC_TIMER4_COUNT 0x4c |
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#define PIC_TIMER5_COUNT 0x4e |
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#define PIC_TIMER6_COUNT 0x50 |
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#define PIC_TIMER7_COUNT 0x52 |
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#define PIC_TIMER_COUNT(i) (PIC_TIMER0_COUNT + ((i) * 2)) |
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#define PIC_ITE0_N0_N1 0x54 |
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#define PIC_ITE1_N0_N1 0x58 |
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#define PIC_ITE2_N0_N1 0x5c |
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#define PIC_ITE3_N0_N1 0x60 |
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#define PIC_ITE4_N0_N1 0x64 |
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#define PIC_ITE5_N0_N1 0x68 |
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#define PIC_ITE6_N0_N1 0x6c |
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#define PIC_ITE7_N0_N1 0x70 |
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#define PIC_ITE_N0_N1(i) (PIC_ITE0_N0_N1 + ((i) * 4)) |
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#define PIC_ITE0_N2_N3 0x56 |
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#define PIC_ITE1_N2_N3 0x5a |
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#define PIC_ITE2_N2_N3 0x5e |
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#define PIC_ITE3_N2_N3 0x62 |
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#define PIC_ITE4_N2_N3 0x66 |
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#define PIC_ITE5_N2_N3 0x6a |
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#define PIC_ITE6_N2_N3 0x6e |
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#define PIC_ITE7_N2_N3 0x72 |
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#define PIC_ITE_N2_N3(i) (PIC_ITE0_N2_N3 + ((i) * 4)) |
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#define PIC_IRT0 0x74 |
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#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2)) |
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#define PIC_9XX_PENDING_0 0x6 |
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#define PIC_9XX_PENDING_1 0x8 |
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#define PIC_9XX_PENDING_2 0xa |
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#define PIC_9XX_PENDING_3 0xc |
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#define PIC_9XX_IRT0 0x1c0 |
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#define PIC_9XX_IRT(i) (PIC_9XX_IRT0 + ((i) * 2)) |
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/* |
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* IRT Map |
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*/ |
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#define PIC_NUM_IRTS 160 |
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#define PIC_9XX_NUM_IRTS 256 |
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#define PIC_IRT_WD_0_INDEX 0 |
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#define PIC_IRT_WD_1_INDEX 1 |
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#define PIC_IRT_WD_NMI_0_INDEX 2 |
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#define PIC_IRT_WD_NMI_1_INDEX 3 |
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#define PIC_IRT_TIMER_0_INDEX 4 |
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#define PIC_IRT_TIMER_1_INDEX 5 |
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#define PIC_IRT_TIMER_2_INDEX 6 |
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#define PIC_IRT_TIMER_3_INDEX 7 |
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#define PIC_IRT_TIMER_4_INDEX 8 |
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#define PIC_IRT_TIMER_5_INDEX 9 |
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#define PIC_IRT_TIMER_6_INDEX 10 |
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#define PIC_IRT_TIMER_7_INDEX 11 |
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#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX |
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#define PIC_IRT_TIMER_INDEX(num) ((num) + PIC_IRT_TIMER_0_INDEX) |
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/* 11 and 12 */ |
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#define PIC_NUM_MSG_Q_IRTS 32 |
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#define PIC_IRT_MSG_Q0_INDEX 12 |
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#define PIC_IRT_MSG_Q_INDEX(qid) ((qid) + PIC_IRT_MSG_Q0_INDEX) |
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/* 12 to 43 */ |
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#define PIC_IRT_MSG_0_INDEX 44 |
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#define PIC_IRT_MSG_1_INDEX 45 |
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/* 44 and 45 */ |
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#define PIC_NUM_PCIE_MSIX_IRTS 32 |
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#define PIC_IRT_PCIE_MSIX_0_INDEX 46 |
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#define PIC_IRT_PCIE_MSIX_INDEX(num) ((num) + PIC_IRT_PCIE_MSIX_0_INDEX) |
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/* 46 to 77 */ |
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#define PIC_NUM_PCIE_LINK_IRTS 4 |
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#define PIC_IRT_PCIE_LINK_0_INDEX 78 |
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#define PIC_IRT_PCIE_LINK_1_INDEX 79 |
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#define PIC_IRT_PCIE_LINK_2_INDEX 80 |
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#define PIC_IRT_PCIE_LINK_3_INDEX 81 |
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#define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX) |
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#define PIC_9XX_IRT_PCIE_LINK_0_INDEX 191 |
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#define PIC_9XX_IRT_PCIE_LINK_INDEX(num) \ |
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((num) + PIC_9XX_IRT_PCIE_LINK_0_INDEX) |
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#define PIC_CLOCK_TIMER 7 |
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#if !defined(LOCORE) && !defined(__ASSEMBLY__) |
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/* |
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* Misc |
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*/ |
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#define PIC_IRT_VALID 1 |
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#define PIC_LOCAL_SCHEDULING 1 |
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#define PIC_GLOBAL_SCHEDULING 0 |
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#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r) |
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#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v) |
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#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \ |
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XLP9XX_IO_PIC_OFFSET(node) : XLP_IO_PIC_OFFSET(node)) |
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#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ) |
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/* We use PIC on node 0 as a timer */ |
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#define pic_timer_freq() nlm_get_pic_frequency(0) |
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/* IRT and h/w interrupt routines */ |
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static inline void |
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nlm_9xx_pic_write_irt(uint64_t base, int irt_num, int en, int nmi, |
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int sch, int vec, int dt, int db, int cpu) |
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{ |
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uint64_t val; |
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val = (((uint64_t)en & 0x1) << 22) | ((nmi & 0x1) << 23) | |
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((0 /*mc*/) << 20) | ((vec & 0x3f) << 24) | |
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((dt & 0x1) << 21) | (0 /*ptr*/ << 16) | |
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(cpu & 0x3ff); |
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nlm_write_pic_reg(base, PIC_9XX_IRT(irt_num), val); |
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} |
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static inline void |
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nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi, |
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int sch, int vec, int dt, int db, int dte) |
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{ |
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uint64_t val; |
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val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) | |
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((sch & 0x1) << 28) | ((vec & 0x3f) << 20) | |
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((dt & 0x1) << 19) | ((db & 0x7) << 16) | |
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(dte & 0xffff); |
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nlm_write_pic_reg(base, PIC_IRT(irt_num), val); |
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} |
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static inline void |
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nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi, |
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int sch, int vec, int cpu) |
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{ |
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if (cpu_is_xlp9xx()) |
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nlm_9xx_pic_write_irt(base, irt_num, en, nmi, sch, vec, |
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1, 0, cpu); |
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else |
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nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1, |
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(cpu >> 4), /* thread group */ |
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1 << (cpu & 0xf)); /* thread mask */ |
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} |
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static inline uint64_t |
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nlm_pic_read_timer(uint64_t base, int timer) |
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{ |
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return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer)); |
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} |
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static inline uint32_t |
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nlm_pic_read_timer32(uint64_t base, int timer) |
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{ |
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return (uint32_t)nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer)); |
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} |
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static inline void |
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nlm_pic_write_timer(uint64_t base, int timer, uint64_t value) |
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{ |
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nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value); |
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} |
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static inline void |
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nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu) |
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{ |
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uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL); |
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int en; |
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en = (irq > 0); |
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nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value); |
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nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer), |
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en, 0, 0, irq, cpu); |
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/* enable the timer */ |
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pic_ctrl |= (1 << (PIC_CTRL_STE + timer)); |
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nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl); |
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} |
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static inline void |
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nlm_pic_enable_irt(uint64_t base, int irt) |
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{ |
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uint64_t reg; |
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if (cpu_is_xlp9xx()) { |
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reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt)); |
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nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg | (1 << 22)); |
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} else { |
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reg = nlm_read_pic_reg(base, PIC_IRT(irt)); |
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nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31)); |
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} |
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} |
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static inline void |
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nlm_pic_disable_irt(uint64_t base, int irt) |
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{ |
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uint64_t reg; |
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if (cpu_is_xlp9xx()) { |
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reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt)); |
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reg &= ~((uint64_t)1 << 22); |
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nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg); |
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} else { |
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reg = nlm_read_pic_reg(base, PIC_IRT(irt)); |
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reg &= ~((uint64_t)1 << 31); |
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nlm_write_pic_reg(base, PIC_IRT(irt), reg); |
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} |
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} |
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static inline void |
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nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi) |
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{ |
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uint64_t ipi; |
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if (cpu_is_xlp9xx()) |
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ipi = (nmi << 23) | (irq << 24) | |
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(0/*mcm*/ << 20) | (0/*ptr*/ << 16) | hwt; |
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else |
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ipi = ((uint64_t)nmi << 31) | (irq << 20) | |
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((hwt >> 4) << 16) | (1 << (hwt & 0xf)); |
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nlm_write_pic_reg(base, PIC_IPI_CTL, ipi); |
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} |
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static inline void |
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nlm_pic_ack(uint64_t base, int irt_num) |
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{ |
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nlm_write_pic_reg(base, PIC_INT_ACK, irt_num); |
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/* Ack the Status register for Watchdog & System timers */ |
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if (irt_num < 12) |
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nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num)); |
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} |
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static inline void |
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nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en) |
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{ |
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nlm_pic_write_irt_direct(base, irt, en, 0, 0, irq, hwt); |
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} |
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int nlm_irq_to_irt(int irq); |
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#endif /* __ASSEMBLY__ */ |
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#endif /* _NLM_HAL_PIC_H */
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