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171 lines
4.6 KiB
171 lines
4.6 KiB
/* |
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights |
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* reserved. |
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* |
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* This software is available to you under a choice of one of two |
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* licenses. You may choose to be licensed under the terms of the GNU |
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* General Public License (GPL) Version 2, available from the file |
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* COPYING in the main directory of this source tree, or the NetLogic |
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* license below: |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* |
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR |
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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#ifndef __NLM_HAL_HALDEFS_H__ |
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#define __NLM_HAL_HALDEFS_H__ |
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#include <linux/irqflags.h> /* for local_irq_disable */ |
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/* |
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* This file contains platform specific memory mapped IO implementation |
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* and will provide a way to read 32/64 bit memory mapped registers in |
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* all ABIs |
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*/ |
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static inline uint32_t |
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nlm_read_reg(uint64_t base, uint32_t reg) |
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{ |
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volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; |
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return *addr; |
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} |
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static inline void |
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nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val) |
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{ |
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volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; |
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*addr = val; |
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} |
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/* |
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* For o32 compilation, we have to disable interrupts to access 64 bit |
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* registers |
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* |
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* We need to disable interrupts because we save just the lower 32 bits of |
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* registers in interrupt handling. So if we get hit by an interrupt while |
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* using the upper 32 bits of a register, we lose. |
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*/ |
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static inline uint64_t |
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nlm_read_reg64(uint64_t base, uint32_t reg) |
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{ |
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uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); |
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volatile uint64_t *ptr = (volatile uint64_t *)(long)addr; |
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uint64_t val; |
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if (sizeof(unsigned long) == 4) { |
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unsigned long flags; |
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local_irq_save(flags); |
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__asm__ __volatile__( |
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".set push" "\n\t" |
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".set mips64" "\n\t" |
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"ld %L0, %1" "\n\t" |
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"dsra32 %M0, %L0, 0" "\n\t" |
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"sll %L0, %L0, 0" "\n\t" |
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".set pop" "\n" |
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: "=r" (val) |
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: "m" (*ptr)); |
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local_irq_restore(flags); |
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} else |
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val = *ptr; |
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return val; |
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} |
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static inline void |
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nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val) |
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{ |
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uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); |
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volatile uint64_t *ptr = (volatile uint64_t *)(long)addr; |
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if (sizeof(unsigned long) == 4) { |
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unsigned long flags; |
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uint64_t tmp; |
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local_irq_save(flags); |
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__asm__ __volatile__( |
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".set push" "\n\t" |
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".set mips64" "\n\t" |
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"dsll32 %L0, %L0, 0" "\n\t" |
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"dsrl32 %L0, %L0, 0" "\n\t" |
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"dsll32 %M0, %M0, 0" "\n\t" |
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"or %L0, %L0, %M0" "\n\t" |
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"sd %L0, %2" "\n\t" |
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".set pop" "\n" |
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: "=r" (tmp) |
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: "0" (val), "m" (*ptr)); |
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local_irq_restore(flags); |
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} else |
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*ptr = val; |
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} |
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/* |
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* Routines to store 32/64 bit values to 64 bit addresses, |
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* used when going thru XKPHYS to access registers |
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*/ |
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static inline uint32_t |
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nlm_read_reg_xkphys(uint64_t base, uint32_t reg) |
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{ |
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return nlm_read_reg(base, reg); |
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} |
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static inline void |
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nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val) |
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{ |
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nlm_write_reg(base, reg, val); |
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} |
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static inline uint64_t |
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nlm_read_reg64_xkphys(uint64_t base, uint32_t reg) |
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{ |
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return nlm_read_reg64(base, reg); |
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} |
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static inline void |
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nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val) |
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{ |
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nlm_write_reg64(base, reg, val); |
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} |
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/* Location where IO base is mapped */ |
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extern uint64_t nlm_io_base; |
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#if defined(CONFIG_CPU_XLP) |
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static inline uint64_t |
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nlm_pcicfg_base(uint32_t devoffset) |
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{ |
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return nlm_io_base + devoffset; |
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} |
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#elif defined(CONFIG_CPU_XLR) |
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static inline uint64_t |
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nlm_mmio_base(uint32_t devoffset) |
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{ |
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return nlm_io_base + devoffset; |
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} |
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#endif |
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#endif
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