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79 lines
2.5 KiB
79 lines
2.5 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Defines of the MIPS boards specific address-MAP, registers, etc. |
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* |
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* Copyright (C) 2000,2012 MIPS Technologies, Inc. |
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* All rights reserved. |
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* Authors: Carsten Langgaard <[email protected]> |
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* Steven J. Hill <[email protected]> |
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*/ |
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#ifndef __ASM_MIPS_BOARDS_GENERIC_H |
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#define __ASM_MIPS_BOARDS_GENERIC_H |
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#include <asm/addrspace.h> |
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#include <asm/byteorder.h> |
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#include <asm/mips-boards/bonito64.h> |
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/* |
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* Display register base. |
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*/ |
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#define ASCII_DISPLAY_WORD_BASE 0x1f000410 |
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#define ASCII_DISPLAY_POS_BASE 0x1f000418 |
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/* |
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* Revision register. |
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*/ |
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#define MIPS_REVISION_REG 0x1fc00010 |
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#define MIPS_REVISION_CORID_QED_RM5261 0 |
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#define MIPS_REVISION_CORID_CORE_LV 1 |
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#define MIPS_REVISION_CORID_BONITO64 2 |
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#define MIPS_REVISION_CORID_CORE_20K 3 |
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#define MIPS_REVISION_CORID_CORE_FPGA 4 |
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#define MIPS_REVISION_CORID_CORE_MSC 5 |
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#define MIPS_REVISION_CORID_CORE_EMUL 6 |
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#define MIPS_REVISION_CORID_CORE_FPGA2 7 |
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#define MIPS_REVISION_CORID_CORE_FPGAR2 8 |
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#define MIPS_REVISION_CORID_CORE_FPGA3 9 |
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#define MIPS_REVISION_CORID_CORE_24K 10 |
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#define MIPS_REVISION_CORID_CORE_FPGA4 11 |
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#define MIPS_REVISION_CORID_CORE_FPGA5 12 |
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/**** Artificial corid defines ****/ |
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/* |
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* CoreEMUL with Bonito System Controller is treated like a Core20K |
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* CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC |
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*/ |
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#define MIPS_REVISION_CORID_CORE_EMUL_BON -1 |
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#define MIPS_REVISION_CORID_CORE_EMUL_MSC -2 |
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#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) |
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#define MIPS_REVISION_SCON_OTHER 0 |
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#define MIPS_REVISION_SCON_SOCITSC 1 |
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#define MIPS_REVISION_SCON_SOCITSCP 2 |
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/* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */ |
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#define MIPS_REVISION_SCON_UNKNOWN -1 |
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#define MIPS_REVISION_SCON_GT64120 -2 |
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#define MIPS_REVISION_SCON_BONITO -3 |
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#define MIPS_REVISION_SCON_BRTL -4 |
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#define MIPS_REVISION_SCON_SOCIT -5 |
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#define MIPS_REVISION_SCON_ROCIT -6 |
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#define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff) |
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extern int mips_revision_sconid; |
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#ifdef CONFIG_PCI |
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extern void mips_pcibios_init(void); |
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#else |
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#define mips_pcibios_init() do { } while (0) |
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#endif |
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extern void mips_scroll_message(void); |
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extern void mips_display_message(const char *str); |
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#endif /* __ASM_MIPS_BOARDS_GENERIC_H */
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