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51 lines
1.3 KiB
51 lines
1.3 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* |
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* Parts of this file are based on Ralink's 2.6.21 BSP |
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* |
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* Copyright (C) 2008-2011 Gabor Juhos <[email protected]> |
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* Copyright (C) 2008 Imre Kaloz <[email protected]> |
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* Copyright (C) 2013 John Crispin <[email protected]> |
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*/ |
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#ifndef _RT288X_REGS_H_ |
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#define _RT288X_REGS_H_ |
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#define RT2880_SYSC_BASE 0x00300000 |
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#define SYSC_REG_CHIP_NAME0 0x00 |
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#define SYSC_REG_CHIP_NAME1 0x04 |
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#define SYSC_REG_CHIP_ID 0x0c |
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#define SYSC_REG_SYSTEM_CONFIG 0x10 |
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#define SYSC_REG_CLKCFG 0x30 |
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#define RT2880_CHIP_NAME0 0x38325452 |
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#define RT2880_CHIP_NAME1 0x20203038 |
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#define CHIP_ID_ID_MASK 0xff |
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#define CHIP_ID_ID_SHIFT 8 |
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#define CHIP_ID_REV_MASK 0xff |
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#define SYSTEM_CONFIG_CPUCLK_SHIFT 20 |
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#define SYSTEM_CONFIG_CPUCLK_MASK 0x3 |
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#define SYSTEM_CONFIG_CPUCLK_250 0x0 |
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#define SYSTEM_CONFIG_CPUCLK_266 0x1 |
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#define SYSTEM_CONFIG_CPUCLK_280 0x2 |
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#define SYSTEM_CONFIG_CPUCLK_300 0x3 |
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#define RT2880_GPIO_MODE_I2C BIT(0) |
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#define RT2880_GPIO_MODE_UART0 BIT(1) |
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#define RT2880_GPIO_MODE_SPI BIT(2) |
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#define RT2880_GPIO_MODE_UART1 BIT(3) |
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#define RT2880_GPIO_MODE_JTAG BIT(4) |
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#define RT2880_GPIO_MODE_MDIO BIT(5) |
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#define RT2880_GPIO_MODE_SDRAM BIT(6) |
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#define RT2880_GPIO_MODE_PCI BIT(7) |
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#define CLKCFG_SRAM_CS_N_WDT BIT(9) |
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#define RT2880_SDRAM_BASE 0x08000000 |
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#define RT2880_MEM_SIZE_MIN 2 |
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#define RT2880_MEM_SIZE_MAX 128 |
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#endif
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