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66 lines
2.6 KiB
66 lines
2.6 KiB
/* |
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* Copyright (C) 2004, 2007 Maciej W. Rozycki |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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*/ |
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#ifndef _ASM_COMPILER_H |
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#define _ASM_COMPILER_H |
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/* |
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* With GCC 4.5 onwards we can use __builtin_unreachable to indicate to the |
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* compiler that a particular code path will never be hit. This allows it to be |
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* optimised out of the generated binary. |
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* |
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* Unfortunately at least GCC 4.6.3 through 7.3.0 inclusive suffer from a bug |
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* that can lead to instructions from beyond an unreachable statement being |
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* incorrectly reordered into earlier delay slots if the unreachable statement |
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* is the only content of a case in a switch statement. This can lead to |
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* seemingly random behaviour, such as invalid memory accesses from incorrectly |
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* reordered loads or stores. See this potential GCC fix for details: |
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* |
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* https://gcc.gnu.org/ml/gcc-patches/2015-09/msg00360.html |
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* |
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* It is unclear whether GCC 8 onwards suffer from the same issue - nothing |
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* relevant is mentioned in GCC 8 release notes and nothing obviously relevant |
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* stands out in GCC commit logs, but these newer GCC versions generate very |
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* different code for the testcase which doesn't exhibit the bug. |
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* |
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* GCC also handles stack allocation suboptimally when calling noreturn |
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* functions or calling __builtin_unreachable(): |
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* |
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* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82365 |
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* |
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* We work around both of these issues by placing a volatile asm statement, |
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* which GCC is prevented from reordering past, prior to __builtin_unreachable |
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* calls. |
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* |
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* The .insn statement is required to ensure that any branches to the |
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* statement, which sadly must be kept due to the asm statement, are known to |
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* be branches to code and satisfy linker requirements for microMIPS kernels. |
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*/ |
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#undef barrier_before_unreachable |
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#define barrier_before_unreachable() asm volatile(".insn") |
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#define GCC_OFF_SMALL_ASM() "ZC" |
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#ifdef CONFIG_CPU_MIPSR6 |
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#define MIPS_ISA_LEVEL "mips64r6" |
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#define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL |
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#define MIPS_ISA_LEVEL_RAW mips64r6 |
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#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW |
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#elif defined(CONFIG_CPU_MIPSR5) |
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#define MIPS_ISA_LEVEL "mips64r5" |
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#define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL |
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#define MIPS_ISA_LEVEL_RAW mips64r5 |
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#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW |
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#else |
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/* MIPS64 is a superset of MIPS32 */ |
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#define MIPS_ISA_LEVEL "mips64r2" |
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#define MIPS_ISA_ARCH_LEVEL "arch=r4000" |
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#define MIPS_ISA_LEVEL_RAW mips64r2 |
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#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW |
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#endif /* CONFIG_CPU_MIPSR6 */ |
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#endif /* _ASM_COMPILER_H */
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