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324 lines
8.5 KiB
324 lines
8.5 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 2003, 06, 07 by Ralf Baechle ([email protected]) |
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*/ |
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#ifndef __ASM_CMPXCHG_H |
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#define __ASM_CMPXCHG_H |
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#include <linux/bug.h> |
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#include <linux/irqflags.h> |
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#include <asm/compiler.h> |
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#include <asm/llsc.h> |
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#include <asm/sync.h> |
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#include <asm/war.h> |
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/* |
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* These functions doesn't exist, so if they are called you'll either: |
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* |
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* - Get an error at compile-time due to __compiletime_error, if supported by |
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* your compiler. |
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* |
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* or: |
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* |
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* - Get an error at link-time due to the call to the missing function. |
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*/ |
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extern unsigned long __cmpxchg_called_with_bad_pointer(void) |
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__compiletime_error("Bad argument size for cmpxchg"); |
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extern unsigned long __cmpxchg64_unsupported(void) |
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__compiletime_error("cmpxchg64 not available; cpu_has_64bits may be false"); |
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extern unsigned long __xchg_called_with_bad_pointer(void) |
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__compiletime_error("Bad argument size for xchg"); |
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#define __xchg_asm(ld, st, m, val) \ |
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({ \ |
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__typeof(*(m)) __ret; \ |
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\ |
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if (kernel_uses_llsc) { \ |
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__asm__ __volatile__( \ |
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" .set push \n" \ |
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" .set noat \n" \ |
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" .set push \n" \ |
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" .set " MIPS_ISA_ARCH_LEVEL " \n" \ |
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" " __SYNC(full, loongson3_war) " \n" \ |
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"1: " ld " %0, %2 # __xchg_asm \n" \ |
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" .set pop \n" \ |
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" move $1, %z3 \n" \ |
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" .set " MIPS_ISA_ARCH_LEVEL " \n" \ |
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" " st " $1, %1 \n" \ |
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"\t" __SC_BEQZ "$1, 1b \n" \ |
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" .set pop \n" \ |
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: "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \ |
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: GCC_OFF_SMALL_ASM() (*m), "Jr" (val) \ |
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: __LLSC_CLOBBER); \ |
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} else { \ |
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unsigned long __flags; \ |
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\ |
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raw_local_irq_save(__flags); \ |
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__ret = *m; \ |
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*m = val; \ |
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raw_local_irq_restore(__flags); \ |
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} \ |
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\ |
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__ret; \ |
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}) |
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extern unsigned long __xchg_small(volatile void *ptr, unsigned long val, |
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unsigned int size); |
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static __always_inline |
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unsigned long __xchg(volatile void *ptr, unsigned long x, int size) |
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{ |
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switch (size) { |
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case 1: |
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case 2: |
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return __xchg_small(ptr, x, size); |
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case 4: |
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return __xchg_asm("ll", "sc", (volatile u32 *)ptr, x); |
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case 8: |
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if (!IS_ENABLED(CONFIG_64BIT)) |
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return __xchg_called_with_bad_pointer(); |
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return __xchg_asm("lld", "scd", (volatile u64 *)ptr, x); |
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default: |
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return __xchg_called_with_bad_pointer(); |
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} |
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} |
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#define xchg(ptr, x) \ |
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({ \ |
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__typeof__(*(ptr)) __res; \ |
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\ |
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/* \ |
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* In the Loongson3 workaround case __xchg_asm() already \ |
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* contains a completion barrier prior to the LL, so we don't \ |
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* need to emit an extra one here. \ |
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*/ \ |
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if (__SYNC_loongson3_war == 0) \ |
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smp_mb__before_llsc(); \ |
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\ |
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__res = (__typeof__(*(ptr))) \ |
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__xchg((ptr), (unsigned long)(x), sizeof(*(ptr))); \ |
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\ |
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smp_llsc_mb(); \ |
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\ |
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__res; \ |
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}) |
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#define __cmpxchg_asm(ld, st, m, old, new) \ |
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({ \ |
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__typeof(*(m)) __ret; \ |
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\ |
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if (kernel_uses_llsc) { \ |
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__asm__ __volatile__( \ |
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" .set push \n" \ |
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" .set noat \n" \ |
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" .set push \n" \ |
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" .set "MIPS_ISA_ARCH_LEVEL" \n" \ |
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" " __SYNC(full, loongson3_war) " \n" \ |
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"1: " ld " %0, %2 # __cmpxchg_asm \n" \ |
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" bne %0, %z3, 2f \n" \ |
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" .set pop \n" \ |
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" move $1, %z4 \n" \ |
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" .set "MIPS_ISA_ARCH_LEVEL" \n" \ |
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" " st " $1, %1 \n" \ |
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"\t" __SC_BEQZ "$1, 1b \n" \ |
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" .set pop \n" \ |
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"2: " __SYNC(full, loongson3_war) " \n" \ |
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: "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \ |
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: GCC_OFF_SMALL_ASM() (*m), "Jr" (old), "Jr" (new) \ |
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: __LLSC_CLOBBER); \ |
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} else { \ |
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unsigned long __flags; \ |
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\ |
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raw_local_irq_save(__flags); \ |
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__ret = *m; \ |
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if (__ret == old) \ |
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*m = new; \ |
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raw_local_irq_restore(__flags); \ |
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} \ |
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\ |
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__ret; \ |
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}) |
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extern unsigned long __cmpxchg_small(volatile void *ptr, unsigned long old, |
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unsigned long new, unsigned int size); |
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static __always_inline |
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unsigned long __cmpxchg(volatile void *ptr, unsigned long old, |
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unsigned long new, unsigned int size) |
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{ |
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switch (size) { |
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case 1: |
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case 2: |
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return __cmpxchg_small(ptr, old, new, size); |
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case 4: |
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return __cmpxchg_asm("ll", "sc", (volatile u32 *)ptr, |
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(u32)old, new); |
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case 8: |
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/* lld/scd are only available for MIPS64 */ |
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if (!IS_ENABLED(CONFIG_64BIT)) |
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return __cmpxchg_called_with_bad_pointer(); |
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return __cmpxchg_asm("lld", "scd", (volatile u64 *)ptr, |
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(u64)old, new); |
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default: |
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return __cmpxchg_called_with_bad_pointer(); |
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} |
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} |
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#define cmpxchg_local(ptr, old, new) \ |
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((__typeof__(*(ptr))) \ |
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__cmpxchg((ptr), \ |
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(unsigned long)(__typeof__(*(ptr)))(old), \ |
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(unsigned long)(__typeof__(*(ptr)))(new), \ |
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sizeof(*(ptr)))) |
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#define cmpxchg(ptr, old, new) \ |
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({ \ |
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__typeof__(*(ptr)) __res; \ |
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\ |
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/* \ |
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* In the Loongson3 workaround case __cmpxchg_asm() already \ |
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* contains a completion barrier prior to the LL, so we don't \ |
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* need to emit an extra one here. \ |
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*/ \ |
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if (__SYNC_loongson3_war == 0) \ |
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smp_mb__before_llsc(); \ |
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\ |
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__res = cmpxchg_local((ptr), (old), (new)); \ |
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\ |
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/* \ |
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* In the Loongson3 workaround case __cmpxchg_asm() already \ |
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* contains a completion barrier after the SC, so we don't \ |
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* need to emit an extra one here. \ |
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*/ \ |
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if (__SYNC_loongson3_war == 0) \ |
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smp_llsc_mb(); \ |
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\ |
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__res; \ |
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}) |
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#ifdef CONFIG_64BIT |
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#define cmpxchg64_local(ptr, o, n) \ |
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({ \ |
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BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ |
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cmpxchg_local((ptr), (o), (n)); \ |
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}) |
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#define cmpxchg64(ptr, o, n) \ |
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({ \ |
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BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ |
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cmpxchg((ptr), (o), (n)); \ |
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}) |
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#else |
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# include <asm-generic/cmpxchg-local.h> |
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# define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) |
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# ifdef CONFIG_SMP |
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static inline unsigned long __cmpxchg64(volatile void *ptr, |
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unsigned long long old, |
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unsigned long long new) |
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{ |
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unsigned long long tmp, ret; |
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unsigned long flags; |
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/* |
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* The assembly below has to combine 32 bit values into a 64 bit |
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* register, and split 64 bit values from one register into two. If we |
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* were to take an interrupt in the middle of this we'd only save the |
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* least significant 32 bits of each register & probably clobber the |
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* most significant 32 bits of the 64 bit values we're using. In order |
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* to avoid this we must disable interrupts. |
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*/ |
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local_irq_save(flags); |
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asm volatile( |
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" .set push \n" |
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" .set " MIPS_ISA_ARCH_LEVEL " \n" |
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/* Load 64 bits from ptr */ |
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" " __SYNC(full, loongson3_war) " \n" |
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"1: lld %L0, %3 # __cmpxchg64 \n" |
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/* |
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* Split the 64 bit value we loaded into the 2 registers that hold the |
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* ret variable. |
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*/ |
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" dsra %M0, %L0, 32 \n" |
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" sll %L0, %L0, 0 \n" |
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/* |
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* Compare ret against old, breaking out of the loop if they don't |
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* match. |
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*/ |
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" bne %M0, %M4, 2f \n" |
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" bne %L0, %L4, 2f \n" |
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/* |
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* Combine the 32 bit halves from the 2 registers that hold the new |
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* variable into a single 64 bit register. |
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*/ |
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# if MIPS_ISA_REV >= 2 |
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" move %L1, %L5 \n" |
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" dins %L1, %M5, 32, 32 \n" |
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# else |
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" dsll %L1, %L5, 32 \n" |
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" dsrl %L1, %L1, 32 \n" |
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" .set noat \n" |
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" dsll $at, %M5, 32 \n" |
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" or %L1, %L1, $at \n" |
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" .set at \n" |
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# endif |
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/* Attempt to store new at ptr */ |
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" scd %L1, %2 \n" |
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/* If we failed, loop! */ |
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"\t" __SC_BEQZ "%L1, 1b \n" |
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" .set pop \n" |
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"2: " __SYNC(full, loongson3_war) " \n" |
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: "=&r"(ret), |
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"=&r"(tmp), |
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"=" GCC_OFF_SMALL_ASM() (*(unsigned long long *)ptr) |
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: GCC_OFF_SMALL_ASM() (*(unsigned long long *)ptr), |
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"r" (old), |
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"r" (new) |
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: "memory"); |
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local_irq_restore(flags); |
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return ret; |
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} |
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# define cmpxchg64(ptr, o, n) ({ \ |
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unsigned long long __old = (__typeof__(*(ptr)))(o); \ |
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unsigned long long __new = (__typeof__(*(ptr)))(n); \ |
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__typeof__(*(ptr)) __res; \ |
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\ |
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/* \ |
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* We can only use cmpxchg64 if we know that the CPU supports \ |
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* 64-bits, ie. lld & scd. Our call to __cmpxchg64_unsupported \ |
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* will cause a build error unless cpu_has_64bits is a \ |
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* compile-time constant 1. \ |
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*/ \ |
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if (cpu_has_64bits && kernel_uses_llsc) { \ |
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smp_mb__before_llsc(); \ |
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__res = __cmpxchg64((ptr), __old, __new); \ |
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smp_llsc_mb(); \ |
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} else { \ |
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__res = __cmpxchg64_unsupported(); \ |
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} \ |
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\ |
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__res; \ |
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}) |
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# else /* !CONFIG_SMP */ |
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# define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n)) |
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# endif /* !CONFIG_SMP */ |
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#endif /* !CONFIG_64BIT */ |
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#endif /* __ASM_CMPXCHG_H */
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