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128 lines
3.0 KiB
128 lines
3.0 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 2011 by Kevin Cernekee ([email protected]) |
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* |
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* Definitions for BMIPS processors |
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*/ |
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#ifndef _ASM_BMIPS_H |
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#define _ASM_BMIPS_H |
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#include <linux/compiler.h> |
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#include <linux/linkage.h> |
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#include <asm/addrspace.h> |
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#include <asm/mipsregs.h> |
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#include <asm/hazards.h> |
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/* NOTE: the CBR register returns a PA, and it can be above 0xff00_0000 */ |
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#define BMIPS_GET_CBR() ((void __iomem *)(CKSEG1 | \ |
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(unsigned long) \ |
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((read_c0_brcm_cbr() >> 18) << 18))) |
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#define BMIPS_RAC_CONFIG 0x00000000 |
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#define BMIPS_RAC_ADDRESS_RANGE 0x00000004 |
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#define BMIPS_RAC_CONFIG_1 0x00000008 |
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#define BMIPS_L2_CONFIG 0x0000000c |
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#define BMIPS_LMB_CONTROL 0x0000001c |
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#define BMIPS_SYSTEM_BASE 0x00000020 |
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#define BMIPS_PERF_GLOBAL_CONTROL 0x00020000 |
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#define BMIPS_PERF_CONTROL_0 0x00020004 |
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#define BMIPS_PERF_CONTROL_1 0x00020008 |
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#define BMIPS_PERF_COUNTER_0 0x00020010 |
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#define BMIPS_PERF_COUNTER_1 0x00020014 |
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#define BMIPS_PERF_COUNTER_2 0x00020018 |
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#define BMIPS_PERF_COUNTER_3 0x0002001c |
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#define BMIPS_RELO_VECTOR_CONTROL_0 0x00030000 |
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#define BMIPS_RELO_VECTOR_CONTROL_1 0x00038000 |
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#define BMIPS_NMI_RESET_VEC 0x80000000 |
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#define BMIPS_WARM_RESTART_VEC 0x80000380 |
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#define ZSCM_REG_BASE 0x97000000 |
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#if !defined(__ASSEMBLY__) |
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#include <linux/cpumask.h> |
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#include <asm/r4kcache.h> |
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#include <asm/smp-ops.h> |
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extern const struct plat_smp_ops bmips43xx_smp_ops; |
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extern const struct plat_smp_ops bmips5000_smp_ops; |
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static inline int register_bmips_smp_ops(void) |
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{ |
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#if IS_ENABLED(CONFIG_CPU_BMIPS) && IS_ENABLED(CONFIG_SMP) |
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switch (current_cpu_type()) { |
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case CPU_BMIPS32: |
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case CPU_BMIPS3300: |
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return register_up_smp_ops(); |
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case CPU_BMIPS4350: |
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case CPU_BMIPS4380: |
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register_smp_ops(&bmips43xx_smp_ops); |
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break; |
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case CPU_BMIPS5000: |
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register_smp_ops(&bmips5000_smp_ops); |
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break; |
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default: |
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return -ENODEV; |
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} |
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return 0; |
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#else |
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return -ENODEV; |
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#endif |
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} |
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extern char bmips_reset_nmi_vec[]; |
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extern char bmips_reset_nmi_vec_end[]; |
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extern char bmips_smp_movevec[]; |
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extern char bmips_smp_int_vec[]; |
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extern char bmips_smp_int_vec_end[]; |
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extern int bmips_smp_enabled; |
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extern int bmips_cpu_offset; |
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extern cpumask_t bmips_booted_mask; |
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extern unsigned long bmips_tp1_irqs; |
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extern void bmips_ebase_setup(void); |
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extern asmlinkage void plat_wired_tlb_setup(void); |
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extern void bmips_cpu_setup(void); |
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static inline unsigned long bmips_read_zscm_reg(unsigned int offset) |
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{ |
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unsigned long ret; |
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barrier(); |
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cache_op(Index_Load_Tag_S, ZSCM_REG_BASE + offset); |
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__sync(); |
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_ssnop(); |
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_ssnop(); |
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_ssnop(); |
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_ssnop(); |
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_ssnop(); |
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_ssnop(); |
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_ssnop(); |
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ret = read_c0_ddatalo(); |
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_ssnop(); |
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return ret; |
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} |
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static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data) |
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{ |
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write_c0_ddatalo(data); |
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_ssnop(); |
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_ssnop(); |
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_ssnop(); |
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cache_op(Index_Store_Tag_S, ZSCM_REG_BASE + offset); |
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_ssnop(); |
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_ssnop(); |
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_ssnop(); |
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barrier(); |
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} |
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#endif /* !defined(__ASSEMBLY__) */ |
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#endif /* _ASM_BMIPS_H */
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