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101 lines
2.8 KiB
101 lines
2.8 KiB
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
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/* |
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* Copyright (C) 2002,2003 Intel Corp. |
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* Jun Nakajima <[email protected]> |
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* Suresh Siddha <[email protected]> |
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*/ |
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#ifndef _ASM_IA64_IA64REGS_H |
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#define _ASM_IA64_IA64REGS_H |
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/* |
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* Register Names for getreg() and setreg(). |
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* |
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* The "magic" numbers happen to match the values used by the Intel compiler's |
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* getreg()/setreg() intrinsics. |
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*/ |
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/* Special Registers */ |
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#define _IA64_REG_IP 1016 /* getreg only */ |
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#define _IA64_REG_PSR 1019 |
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#define _IA64_REG_PSR_L 1019 |
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/* General Integer Registers */ |
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#define _IA64_REG_GP 1025 /* R1 */ |
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#define _IA64_REG_R8 1032 /* R8 */ |
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#define _IA64_REG_R9 1033 /* R9 */ |
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#define _IA64_REG_SP 1036 /* R12 */ |
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#define _IA64_REG_TP 1037 /* R13 */ |
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/* Application Registers */ |
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#define _IA64_REG_AR_KR0 3072 |
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#define _IA64_REG_AR_KR1 3073 |
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#define _IA64_REG_AR_KR2 3074 |
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#define _IA64_REG_AR_KR3 3075 |
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#define _IA64_REG_AR_KR4 3076 |
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#define _IA64_REG_AR_KR5 3077 |
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#define _IA64_REG_AR_KR6 3078 |
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#define _IA64_REG_AR_KR7 3079 |
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#define _IA64_REG_AR_RSC 3088 |
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#define _IA64_REG_AR_BSP 3089 |
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#define _IA64_REG_AR_BSPSTORE 3090 |
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#define _IA64_REG_AR_RNAT 3091 |
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#define _IA64_REG_AR_FCR 3093 |
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#define _IA64_REG_AR_EFLAG 3096 |
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#define _IA64_REG_AR_CSD 3097 |
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#define _IA64_REG_AR_SSD 3098 |
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#define _IA64_REG_AR_CFLAG 3099 |
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#define _IA64_REG_AR_FSR 3100 |
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#define _IA64_REG_AR_FIR 3101 |
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#define _IA64_REG_AR_FDR 3102 |
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#define _IA64_REG_AR_CCV 3104 |
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#define _IA64_REG_AR_UNAT 3108 |
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#define _IA64_REG_AR_FPSR 3112 |
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#define _IA64_REG_AR_ITC 3116 |
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#define _IA64_REG_AR_PFS 3136 |
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#define _IA64_REG_AR_LC 3137 |
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#define _IA64_REG_AR_EC 3138 |
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/* Control Registers */ |
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#define _IA64_REG_CR_DCR 4096 |
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#define _IA64_REG_CR_ITM 4097 |
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#define _IA64_REG_CR_IVA 4098 |
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#define _IA64_REG_CR_PTA 4104 |
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#define _IA64_REG_CR_IPSR 4112 |
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#define _IA64_REG_CR_ISR 4113 |
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#define _IA64_REG_CR_IIP 4115 |
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#define _IA64_REG_CR_IFA 4116 |
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#define _IA64_REG_CR_ITIR 4117 |
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#define _IA64_REG_CR_IIPA 4118 |
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#define _IA64_REG_CR_IFS 4119 |
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#define _IA64_REG_CR_IIM 4120 |
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#define _IA64_REG_CR_IHA 4121 |
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#define _IA64_REG_CR_LID 4160 |
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#define _IA64_REG_CR_IVR 4161 /* getreg only */ |
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#define _IA64_REG_CR_TPR 4162 |
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#define _IA64_REG_CR_EOI 4163 |
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#define _IA64_REG_CR_IRR0 4164 /* getreg only */ |
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#define _IA64_REG_CR_IRR1 4165 /* getreg only */ |
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#define _IA64_REG_CR_IRR2 4166 /* getreg only */ |
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#define _IA64_REG_CR_IRR3 4167 /* getreg only */ |
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#define _IA64_REG_CR_ITV 4168 |
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#define _IA64_REG_CR_PMV 4169 |
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#define _IA64_REG_CR_CMCV 4170 |
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#define _IA64_REG_CR_LRR0 4176 |
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#define _IA64_REG_CR_LRR1 4177 |
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/* Indirect Registers for getindreg() and setindreg() */ |
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#define _IA64_REG_INDR_CPUID 9000 /* getindreg only */ |
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#define _IA64_REG_INDR_DBR 9001 |
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#define _IA64_REG_INDR_IBR 9002 |
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#define _IA64_REG_INDR_PKR 9003 |
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#define _IA64_REG_INDR_PMC 9004 |
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#define _IA64_REG_INDR_PMD 9005 |
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#define _IA64_REG_INDR_RR 9006 |
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#endif /* _ASM_IA64_IA64REGS_H */
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