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307 lines
7.6 KiB
307 lines
7.6 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright (C) 2015 Masahiro Yamada <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/console.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include "8250.h" |
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/* |
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* This hardware is similar to 8250, but its register map is a bit different: |
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* - MMIO32 (regshift = 2) |
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* - FCR is not at 2, but 3 |
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* - LCR and MCR are not at 3 and 4, they share 4 |
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* - No SCR (Instead, CHAR can be used as a scratch register) |
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* - Divisor latch at 9, no divisor latch access bit |
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*/ |
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#define UNIPHIER_UART_REGSHIFT 2 |
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/* bit[15:8] = CHAR, bit[7:0] = FCR */ |
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#define UNIPHIER_UART_CHAR_FCR (3 << (UNIPHIER_UART_REGSHIFT)) |
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/* bit[15:8] = LCR, bit[7:0] = MCR */ |
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#define UNIPHIER_UART_LCR_MCR (4 << (UNIPHIER_UART_REGSHIFT)) |
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/* Divisor Latch Register */ |
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#define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) |
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struct uniphier8250_priv { |
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int line; |
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struct clk *clk; |
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spinlock_t atomic_write_lock; |
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}; |
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#ifdef CONFIG_SERIAL_8250_CONSOLE |
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static int __init uniphier_early_console_setup(struct earlycon_device *device, |
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const char *options) |
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{ |
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if (!device->port.membase) |
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return -ENODEV; |
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/* This hardware always expects MMIO32 register interface. */ |
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device->port.iotype = UPIO_MEM32; |
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device->port.regshift = UNIPHIER_UART_REGSHIFT; |
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/* |
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* Do not touch the divisor register in early_serial8250_setup(); |
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* we assume it has been initialized by a boot loader. |
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*/ |
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device->baud = 0; |
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return early_serial8250_setup(device, options); |
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} |
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OF_EARLYCON_DECLARE(uniphier, "socionext,uniphier-uart", |
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uniphier_early_console_setup); |
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#endif |
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/* |
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* The register map is slightly different from that of 8250. |
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* IO callbacks must be overridden for correct access to FCR, LCR, MCR and SCR. |
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*/ |
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static unsigned int uniphier_serial_in(struct uart_port *p, int offset) |
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{ |
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unsigned int valshift = 0; |
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switch (offset) { |
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case UART_SCR: |
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/* No SCR for this hardware. Use CHAR as a scratch register */ |
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valshift = 8; |
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offset = UNIPHIER_UART_CHAR_FCR; |
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break; |
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case UART_LCR: |
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valshift = 8; |
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fallthrough; |
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case UART_MCR: |
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offset = UNIPHIER_UART_LCR_MCR; |
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break; |
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default: |
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offset <<= UNIPHIER_UART_REGSHIFT; |
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break; |
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} |
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/* |
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* The return value must be masked with 0xff because some registers |
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* share the same offset that must be accessed by 32-bit write/read. |
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* 8 or 16 bit access to this hardware result in unexpected behavior. |
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*/ |
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return (readl(p->membase + offset) >> valshift) & 0xff; |
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} |
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static void uniphier_serial_out(struct uart_port *p, int offset, int value) |
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{ |
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unsigned int valshift = 0; |
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bool normal = false; |
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switch (offset) { |
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case UART_SCR: |
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/* No SCR for this hardware. Use CHAR as a scratch register */ |
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valshift = 8; |
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fallthrough; |
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case UART_FCR: |
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offset = UNIPHIER_UART_CHAR_FCR; |
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break; |
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case UART_LCR: |
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valshift = 8; |
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/* Divisor latch access bit does not exist. */ |
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value &= ~UART_LCR_DLAB; |
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fallthrough; |
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case UART_MCR: |
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offset = UNIPHIER_UART_LCR_MCR; |
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break; |
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default: |
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offset <<= UNIPHIER_UART_REGSHIFT; |
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normal = true; |
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break; |
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} |
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if (normal) { |
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writel(value, p->membase + offset); |
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} else { |
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/* |
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* Special case: two registers share the same address that |
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* must be 32-bit accessed. As this is not longer atomic safe, |
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* take a lock just in case. |
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*/ |
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struct uniphier8250_priv *priv = p->private_data; |
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unsigned long flags; |
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u32 tmp; |
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spin_lock_irqsave(&priv->atomic_write_lock, flags); |
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tmp = readl(p->membase + offset); |
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tmp &= ~(0xff << valshift); |
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tmp |= value << valshift; |
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writel(tmp, p->membase + offset); |
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spin_unlock_irqrestore(&priv->atomic_write_lock, flags); |
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} |
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} |
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/* |
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* This hardware does not have the divisor latch access bit. |
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* The divisor latch register exists at different address. |
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* Override dl_read/write callbacks. |
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*/ |
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static int uniphier_serial_dl_read(struct uart_8250_port *up) |
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{ |
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return readl(up->port.membase + UNIPHIER_UART_DLR); |
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} |
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static void uniphier_serial_dl_write(struct uart_8250_port *up, int value) |
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{ |
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writel(value, up->port.membase + UNIPHIER_UART_DLR); |
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} |
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static int uniphier_uart_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct uart_8250_port up; |
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struct uniphier8250_priv *priv; |
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struct resource *regs; |
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void __iomem *membase; |
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int irq; |
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int ret; |
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (!regs) { |
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dev_err(dev, "failed to get memory resource\n"); |
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return -EINVAL; |
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} |
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membase = devm_ioremap(dev, regs->start, resource_size(regs)); |
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if (!membase) |
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return -ENOMEM; |
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irq = platform_get_irq(pdev, 0); |
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if (irq < 0) |
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return irq; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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memset(&up, 0, sizeof(up)); |
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ret = of_alias_get_id(dev->of_node, "serial"); |
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if (ret < 0) { |
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dev_err(dev, "failed to get alias id\n"); |
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return ret; |
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} |
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up.port.line = ret; |
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priv->clk = devm_clk_get(dev, NULL); |
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if (IS_ERR(priv->clk)) { |
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dev_err(dev, "failed to get clock\n"); |
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return PTR_ERR(priv->clk); |
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} |
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ret = clk_prepare_enable(priv->clk); |
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if (ret) |
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return ret; |
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up.port.uartclk = clk_get_rate(priv->clk); |
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spin_lock_init(&priv->atomic_write_lock); |
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up.port.dev = dev; |
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up.port.private_data = priv; |
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up.port.mapbase = regs->start; |
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up.port.mapsize = resource_size(regs); |
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up.port.membase = membase; |
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up.port.irq = irq; |
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up.port.type = PORT_16550A; |
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up.port.iotype = UPIO_MEM32; |
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up.port.fifosize = 64; |
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up.port.regshift = UNIPHIER_UART_REGSHIFT; |
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up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE; |
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up.capabilities = UART_CAP_FIFO; |
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if (of_property_read_bool(dev->of_node, "auto-flow-control")) |
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up.capabilities |= UART_CAP_AFE; |
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up.port.serial_in = uniphier_serial_in; |
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up.port.serial_out = uniphier_serial_out; |
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up.dl_read = uniphier_serial_dl_read; |
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up.dl_write = uniphier_serial_dl_write; |
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ret = serial8250_register_8250_port(&up); |
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if (ret < 0) { |
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dev_err(dev, "failed to register 8250 port\n"); |
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clk_disable_unprepare(priv->clk); |
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return ret; |
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} |
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priv->line = ret; |
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platform_set_drvdata(pdev, priv); |
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return 0; |
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} |
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static int uniphier_uart_remove(struct platform_device *pdev) |
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{ |
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struct uniphier8250_priv *priv = platform_get_drvdata(pdev); |
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serial8250_unregister_port(priv->line); |
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clk_disable_unprepare(priv->clk); |
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return 0; |
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} |
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static int __maybe_unused uniphier_uart_suspend(struct device *dev) |
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{ |
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struct uniphier8250_priv *priv = dev_get_drvdata(dev); |
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struct uart_8250_port *up = serial8250_get_port(priv->line); |
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serial8250_suspend_port(priv->line); |
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if (!uart_console(&up->port) || console_suspend_enabled) |
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clk_disable_unprepare(priv->clk); |
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return 0; |
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} |
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static int __maybe_unused uniphier_uart_resume(struct device *dev) |
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{ |
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struct uniphier8250_priv *priv = dev_get_drvdata(dev); |
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struct uart_8250_port *up = serial8250_get_port(priv->line); |
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int ret; |
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if (!uart_console(&up->port) || console_suspend_enabled) { |
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ret = clk_prepare_enable(priv->clk); |
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if (ret) |
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return ret; |
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} |
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serial8250_resume_port(priv->line); |
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return 0; |
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} |
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static const struct dev_pm_ops uniphier_uart_pm_ops = { |
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SET_SYSTEM_SLEEP_PM_OPS(uniphier_uart_suspend, uniphier_uart_resume) |
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}; |
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static const struct of_device_id uniphier_uart_match[] = { |
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{ .compatible = "socionext,uniphier-uart" }, |
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{ /* sentinel */ } |
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}; |
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MODULE_DEVICE_TABLE(of, uniphier_uart_match); |
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static struct platform_driver uniphier_uart_platform_driver = { |
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.probe = uniphier_uart_probe, |
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.remove = uniphier_uart_remove, |
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.driver = { |
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.name = "uniphier-uart", |
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.of_match_table = uniphier_uart_match, |
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.pm = &uniphier_uart_pm_ops, |
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}, |
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}; |
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module_platform_driver(uniphier_uart_platform_driver); |
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MODULE_AUTHOR("Masahiro Yamada <[email protected]>"); |
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MODULE_DESCRIPTION("UniPhier UART driver"); |
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MODULE_LICENSE("GPL");
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