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219 lines
6.1 KiB
219 lines
6.1 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Serial port driver for BCM2835AUX UART |
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* |
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* Copyright (C) 2016 Martin Sperl <[email protected]> |
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* |
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* Based on 8250_lpc18xx.c: |
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* Copyright (C) 2015 Joachim Eastwood <[email protected]> |
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* |
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* The bcm2835aux is capable of RTS auto flow-control, but this driver doesn't |
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* take advantage of it yet. When adding support, be sure not to enable it |
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* simultaneously to rs485. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include "8250.h" |
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#define BCM2835_AUX_UART_CNTL 8 |
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#define BCM2835_AUX_UART_CNTL_RXEN 0x01 /* Receiver enable */ |
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#define BCM2835_AUX_UART_CNTL_TXEN 0x02 /* Transmitter enable */ |
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#define BCM2835_AUX_UART_CNTL_AUTORTS 0x04 /* RTS set by RX fill level */ |
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#define BCM2835_AUX_UART_CNTL_AUTOCTS 0x08 /* CTS stops transmitter */ |
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#define BCM2835_AUX_UART_CNTL_RTS3 0x00 /* RTS set until 3 chars left */ |
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#define BCM2835_AUX_UART_CNTL_RTS2 0x10 /* RTS set until 2 chars left */ |
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#define BCM2835_AUX_UART_CNTL_RTS1 0x20 /* RTS set until 1 chars left */ |
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#define BCM2835_AUX_UART_CNTL_RTS4 0x30 /* RTS set until 4 chars left */ |
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#define BCM2835_AUX_UART_CNTL_RTSINV 0x40 /* Invert auto RTS polarity */ |
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#define BCM2835_AUX_UART_CNTL_CTSINV 0x80 /* Invert auto CTS polarity */ |
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/** |
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* struct bcm2835aux_data - driver private data of BCM2835 auxiliary UART |
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* @clk: clock producer of the port's uartclk |
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* @line: index of the port's serial8250_ports[] entry |
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* @cntl: cached copy of CNTL register |
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*/ |
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struct bcm2835aux_data { |
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struct clk *clk; |
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int line; |
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u32 cntl; |
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}; |
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static void bcm2835aux_rs485_start_tx(struct uart_8250_port *up) |
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{ |
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if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) { |
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struct bcm2835aux_data *data = dev_get_drvdata(up->port.dev); |
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data->cntl &= ~BCM2835_AUX_UART_CNTL_RXEN; |
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serial_out(up, BCM2835_AUX_UART_CNTL, data->cntl); |
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} |
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/* |
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* On the bcm2835aux, the MCR register contains no other |
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* flags besides RTS. So no need for a read-modify-write. |
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*/ |
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if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND) |
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serial8250_out_MCR(up, 0); |
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else |
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serial8250_out_MCR(up, UART_MCR_RTS); |
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} |
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static void bcm2835aux_rs485_stop_tx(struct uart_8250_port *up) |
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{ |
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if (up->port.rs485.flags & SER_RS485_RTS_AFTER_SEND) |
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serial8250_out_MCR(up, 0); |
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else |
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serial8250_out_MCR(up, UART_MCR_RTS); |
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if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) { |
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struct bcm2835aux_data *data = dev_get_drvdata(up->port.dev); |
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data->cntl |= BCM2835_AUX_UART_CNTL_RXEN; |
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serial_out(up, BCM2835_AUX_UART_CNTL, data->cntl); |
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} |
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} |
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static int bcm2835aux_serial_probe(struct platform_device *pdev) |
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{ |
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struct uart_8250_port up = { }; |
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struct bcm2835aux_data *data; |
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struct resource *res; |
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int ret; |
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/* allocate the custom structure */ |
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data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); |
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if (!data) |
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return -ENOMEM; |
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/* initialize data */ |
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up.capabilities = UART_CAP_FIFO | UART_CAP_MINI; |
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up.port.dev = &pdev->dev; |
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up.port.regshift = 2; |
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up.port.type = PORT_16550; |
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up.port.iotype = UPIO_MEM; |
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up.port.fifosize = 8; |
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up.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT | UPF_FIXED_TYPE | |
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UPF_SKIP_TEST | UPF_IOREMAP; |
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up.port.rs485_config = serial8250_em485_config; |
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up.rs485_start_tx = bcm2835aux_rs485_start_tx; |
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up.rs485_stop_tx = bcm2835aux_rs485_stop_tx; |
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/* initialize cached copy with power-on reset value */ |
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data->cntl = BCM2835_AUX_UART_CNTL_RXEN | BCM2835_AUX_UART_CNTL_TXEN; |
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platform_set_drvdata(pdev, data); |
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/* get the clock - this also enables the HW */ |
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data->clk = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(data->clk)) |
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return dev_err_probe(&pdev->dev, PTR_ERR(data->clk), "could not get clk\n"); |
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/* get the interrupt */ |
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ret = platform_get_irq(pdev, 0); |
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if (ret < 0) |
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return ret; |
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up.port.irq = ret; |
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/* map the main registers */ |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (!res) { |
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dev_err(&pdev->dev, "memory resource not found"); |
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return -EINVAL; |
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} |
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up.port.mapbase = res->start; |
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up.port.mapsize = resource_size(res); |
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/* Check for a fixed line number */ |
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ret = of_alias_get_id(pdev->dev.of_node, "serial"); |
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if (ret >= 0) |
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up.port.line = ret; |
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/* enable the clock as a last step */ |
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ret = clk_prepare_enable(data->clk); |
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if (ret) { |
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dev_err(&pdev->dev, "unable to enable uart clock - %d\n", |
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ret); |
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return ret; |
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} |
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/* the HW-clock divider for bcm2835aux is 8, |
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* but 8250 expects a divider of 16, |
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* so we have to multiply the actual clock by 2 |
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* to get identical baudrates. |
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*/ |
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up.port.uartclk = clk_get_rate(data->clk) * 2; |
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/* The clock is only queried at probe time, which means we get one shot |
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* at this. A zero clock is never going to work and is almost certainly |
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* due to a parent not being ready, so prefer to defer. |
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*/ |
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if (!up.port.uartclk) |
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return -EPROBE_DEFER; |
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/* register the port */ |
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ret = serial8250_register_8250_port(&up); |
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if (ret < 0) { |
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dev_err_probe(&pdev->dev, ret, "unable to register 8250 port\n"); |
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goto dis_clk; |
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} |
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data->line = ret; |
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return 0; |
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dis_clk: |
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clk_disable_unprepare(data->clk); |
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return ret; |
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} |
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static int bcm2835aux_serial_remove(struct platform_device *pdev) |
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{ |
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struct bcm2835aux_data *data = platform_get_drvdata(pdev); |
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serial8250_unregister_port(data->line); |
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clk_disable_unprepare(data->clk); |
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return 0; |
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} |
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static const struct of_device_id bcm2835aux_serial_match[] = { |
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{ .compatible = "brcm,bcm2835-aux-uart" }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, bcm2835aux_serial_match); |
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static struct platform_driver bcm2835aux_serial_driver = { |
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.driver = { |
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.name = "bcm2835-aux-uart", |
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.of_match_table = bcm2835aux_serial_match, |
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}, |
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.probe = bcm2835aux_serial_probe, |
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.remove = bcm2835aux_serial_remove, |
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}; |
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module_platform_driver(bcm2835aux_serial_driver); |
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#ifdef CONFIG_SERIAL_8250_CONSOLE |
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static int __init early_bcm2835aux_setup(struct earlycon_device *device, |
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const char *options) |
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{ |
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if (!device->port.membase) |
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return -ENODEV; |
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device->port.iotype = UPIO_MEM32; |
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device->port.regshift = 2; |
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return early_serial8250_setup(device, NULL); |
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} |
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OF_EARLYCON_DECLARE(bcm2835aux, "brcm,bcm2835-aux-uart", |
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early_bcm2835aux_setup); |
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#endif |
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MODULE_DESCRIPTION("BCM2835 auxiliar UART driver"); |
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MODULE_AUTHOR("Martin Sperl <[email protected]>"); |
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MODULE_LICENSE("GPL v2");
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