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291 lines
7.6 KiB
291 lines
7.6 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// Copyright (c) 2019 Nuvoton Technology corporation. |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/init.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/reboot.h> |
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#include <linux/reset-controller.h> |
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#include <linux/spinlock.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/regmap.h> |
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#include <linux/of_address.h> |
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/* NPCM7xx GCR registers */ |
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#define NPCM_MDLR_OFFSET 0x7C |
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#define NPCM_MDLR_USBD0 BIT(9) |
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#define NPCM_MDLR_USBD1 BIT(8) |
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#define NPCM_MDLR_USBD2_4 BIT(21) |
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#define NPCM_MDLR_USBD5_9 BIT(22) |
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#define NPCM_USB1PHYCTL_OFFSET 0x140 |
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#define NPCM_USB2PHYCTL_OFFSET 0x144 |
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#define NPCM_USBXPHYCTL_RS BIT(28) |
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/* NPCM7xx Reset registers */ |
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#define NPCM_SWRSTR 0x14 |
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#define NPCM_SWRST BIT(2) |
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#define NPCM_IPSRST1 0x20 |
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#define NPCM_IPSRST1_USBD1 BIT(5) |
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#define NPCM_IPSRST1_USBD2 BIT(8) |
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#define NPCM_IPSRST1_USBD3 BIT(25) |
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#define NPCM_IPSRST1_USBD4 BIT(22) |
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#define NPCM_IPSRST1_USBD5 BIT(23) |
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#define NPCM_IPSRST1_USBD6 BIT(24) |
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#define NPCM_IPSRST2 0x24 |
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#define NPCM_IPSRST2_USB_HOST BIT(26) |
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#define NPCM_IPSRST3 0x34 |
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#define NPCM_IPSRST3_USBD0 BIT(4) |
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#define NPCM_IPSRST3_USBD7 BIT(5) |
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#define NPCM_IPSRST3_USBD8 BIT(6) |
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#define NPCM_IPSRST3_USBD9 BIT(7) |
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#define NPCM_IPSRST3_USBPHY1 BIT(24) |
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#define NPCM_IPSRST3_USBPHY2 BIT(25) |
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#define NPCM_RC_RESETS_PER_REG 32 |
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#define NPCM_MASK_RESETS GENMASK(4, 0) |
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struct npcm_rc_data { |
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struct reset_controller_dev rcdev; |
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struct notifier_block restart_nb; |
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u32 sw_reset_number; |
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void __iomem *base; |
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spinlock_t lock; |
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}; |
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#define to_rc_data(p) container_of(p, struct npcm_rc_data, rcdev) |
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static int npcm_rc_restart(struct notifier_block *nb, unsigned long mode, |
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void *cmd) |
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{ |
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struct npcm_rc_data *rc = container_of(nb, struct npcm_rc_data, |
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restart_nb); |
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writel(NPCM_SWRST << rc->sw_reset_number, rc->base + NPCM_SWRSTR); |
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mdelay(1000); |
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pr_emerg("%s: unable to restart system\n", __func__); |
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return NOTIFY_DONE; |
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} |
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static int npcm_rc_setclear_reset(struct reset_controller_dev *rcdev, |
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unsigned long id, bool set) |
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{ |
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struct npcm_rc_data *rc = to_rc_data(rcdev); |
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unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS); |
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unsigned int ctrl_offset = id >> 8; |
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unsigned long flags; |
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u32 stat; |
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spin_lock_irqsave(&rc->lock, flags); |
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stat = readl(rc->base + ctrl_offset); |
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if (set) |
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writel(stat | rst_bit, rc->base + ctrl_offset); |
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else |
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writel(stat & ~rst_bit, rc->base + ctrl_offset); |
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spin_unlock_irqrestore(&rc->lock, flags); |
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return 0; |
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} |
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static int npcm_rc_assert(struct reset_controller_dev *rcdev, unsigned long id) |
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{ |
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return npcm_rc_setclear_reset(rcdev, id, true); |
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} |
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static int npcm_rc_deassert(struct reset_controller_dev *rcdev, |
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unsigned long id) |
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{ |
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return npcm_rc_setclear_reset(rcdev, id, false); |
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} |
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static int npcm_rc_status(struct reset_controller_dev *rcdev, |
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unsigned long id) |
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{ |
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struct npcm_rc_data *rc = to_rc_data(rcdev); |
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unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS); |
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unsigned int ctrl_offset = id >> 8; |
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return (readl(rc->base + ctrl_offset) & rst_bit); |
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} |
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static int npcm_reset_xlate(struct reset_controller_dev *rcdev, |
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const struct of_phandle_args *reset_spec) |
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{ |
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unsigned int offset, bit; |
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offset = reset_spec->args[0]; |
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if (offset != NPCM_IPSRST1 && offset != NPCM_IPSRST2 && |
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offset != NPCM_IPSRST3) { |
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dev_err(rcdev->dev, "Error reset register (0x%x)\n", offset); |
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return -EINVAL; |
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} |
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bit = reset_spec->args[1]; |
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if (bit >= NPCM_RC_RESETS_PER_REG) { |
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dev_err(rcdev->dev, "Error reset number (%d)\n", bit); |
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return -EINVAL; |
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} |
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return (offset << 8) | bit; |
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} |
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static const struct of_device_id npcm_rc_match[] = { |
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{ .compatible = "nuvoton,npcm750-reset", |
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.data = (void *)"nuvoton,npcm750-gcr" }, |
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{ } |
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}; |
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/* |
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* The following procedure should be observed in USB PHY, USB device and |
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* USB host initialization at BMC boot |
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*/ |
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static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc) |
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{ |
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u32 mdlr, iprst1, iprst2, iprst3; |
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struct device *dev = &pdev->dev; |
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struct regmap *gcr_regmap; |
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u32 ipsrst1_bits = 0; |
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u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST; |
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u32 ipsrst3_bits = 0; |
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const char *gcr_dt; |
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gcr_dt = (const char *) |
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of_match_device(dev->driver->of_match_table, dev)->data; |
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gcr_regmap = syscon_regmap_lookup_by_compatible(gcr_dt); |
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if (IS_ERR(gcr_regmap)) { |
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dev_err(&pdev->dev, "Failed to find %s\n", gcr_dt); |
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return PTR_ERR(gcr_regmap); |
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} |
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/* checking which USB device is enabled */ |
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regmap_read(gcr_regmap, NPCM_MDLR_OFFSET, &mdlr); |
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if (!(mdlr & NPCM_MDLR_USBD0)) |
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ipsrst3_bits |= NPCM_IPSRST3_USBD0; |
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if (!(mdlr & NPCM_MDLR_USBD1)) |
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ipsrst1_bits |= NPCM_IPSRST1_USBD1; |
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if (!(mdlr & NPCM_MDLR_USBD2_4)) |
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ipsrst1_bits |= (NPCM_IPSRST1_USBD2 | |
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NPCM_IPSRST1_USBD3 | |
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NPCM_IPSRST1_USBD4); |
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if (!(mdlr & NPCM_MDLR_USBD0)) { |
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ipsrst1_bits |= (NPCM_IPSRST1_USBD5 | |
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NPCM_IPSRST1_USBD6); |
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ipsrst3_bits |= (NPCM_IPSRST3_USBD7 | |
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NPCM_IPSRST3_USBD8 | |
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NPCM_IPSRST3_USBD9); |
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} |
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/* assert reset USB PHY and USB devices */ |
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iprst1 = readl(rc->base + NPCM_IPSRST1); |
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iprst2 = readl(rc->base + NPCM_IPSRST2); |
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iprst3 = readl(rc->base + NPCM_IPSRST3); |
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iprst1 |= ipsrst1_bits; |
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iprst2 |= ipsrst2_bits; |
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iprst3 |= (ipsrst3_bits | NPCM_IPSRST3_USBPHY1 | |
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NPCM_IPSRST3_USBPHY2); |
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writel(iprst1, rc->base + NPCM_IPSRST1); |
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writel(iprst2, rc->base + NPCM_IPSRST2); |
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writel(iprst3, rc->base + NPCM_IPSRST3); |
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/* clear USB PHY RS bit */ |
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regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET, |
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NPCM_USBXPHYCTL_RS, 0); |
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regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET, |
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NPCM_USBXPHYCTL_RS, 0); |
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/* deassert reset USB PHY */ |
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iprst3 &= ~(NPCM_IPSRST3_USBPHY1 | NPCM_IPSRST3_USBPHY2); |
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writel(iprst3, rc->base + NPCM_IPSRST3); |
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udelay(50); |
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/* set USB PHY RS bit */ |
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regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET, |
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NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS); |
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regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET, |
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NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS); |
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/* deassert reset USB devices*/ |
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iprst1 &= ~ipsrst1_bits; |
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iprst2 &= ~ipsrst2_bits; |
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iprst3 &= ~ipsrst3_bits; |
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writel(iprst1, rc->base + NPCM_IPSRST1); |
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writel(iprst2, rc->base + NPCM_IPSRST2); |
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writel(iprst3, rc->base + NPCM_IPSRST3); |
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return 0; |
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} |
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static const struct reset_control_ops npcm_rc_ops = { |
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.assert = npcm_rc_assert, |
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.deassert = npcm_rc_deassert, |
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.status = npcm_rc_status, |
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}; |
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static int npcm_rc_probe(struct platform_device *pdev) |
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{ |
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struct npcm_rc_data *rc; |
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int ret; |
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rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL); |
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if (!rc) |
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return -ENOMEM; |
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rc->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(rc->base)) |
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return PTR_ERR(rc->base); |
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spin_lock_init(&rc->lock); |
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rc->rcdev.owner = THIS_MODULE; |
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rc->rcdev.ops = &npcm_rc_ops; |
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rc->rcdev.of_node = pdev->dev.of_node; |
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rc->rcdev.of_reset_n_cells = 2; |
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rc->rcdev.of_xlate = npcm_reset_xlate; |
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platform_set_drvdata(pdev, rc); |
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ret = devm_reset_controller_register(&pdev->dev, &rc->rcdev); |
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if (ret) { |
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dev_err(&pdev->dev, "unable to register device\n"); |
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return ret; |
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} |
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if (npcm_usb_reset(pdev, rc)) |
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dev_warn(&pdev->dev, "NPCM USB reset failed, can cause issues with UDC and USB host\n"); |
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if (!of_property_read_u32(pdev->dev.of_node, "nuvoton,sw-reset-number", |
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&rc->sw_reset_number)) { |
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if (rc->sw_reset_number && rc->sw_reset_number < 5) { |
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rc->restart_nb.priority = 192, |
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rc->restart_nb.notifier_call = npcm_rc_restart, |
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ret = register_restart_handler(&rc->restart_nb); |
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if (ret) |
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dev_warn(&pdev->dev, "failed to register restart handler\n"); |
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} |
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} |
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return ret; |
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} |
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static struct platform_driver npcm_rc_driver = { |
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.probe = npcm_rc_probe, |
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.driver = { |
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.name = "npcm-reset", |
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.of_match_table = npcm_rc_match, |
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.suppress_bind_attrs = true, |
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}, |
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}; |
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builtin_platform_driver(npcm_rc_driver);
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