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389 lines
11 KiB
389 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Ingenic SoCs USB PHY driver |
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* Copyright (c) Paul Cercueil <[email protected]> |
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* Copyright (c) 漆鹏振 (Qi Pengzhen) <[email protected]> |
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* Copyright (c) 周琰杰 (Zhou Yanjie) <[email protected]> |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/regulator/consumer.h> |
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/* OTGPHY register offsets */ |
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#define REG_USBPCR_OFFSET 0x00 |
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#define REG_USBRDT_OFFSET 0x04 |
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#define REG_USBVBFIL_OFFSET 0x08 |
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#define REG_USBPCR1_OFFSET 0x0c |
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/* bits within the USBPCR register */ |
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#define USBPCR_USB_MODE BIT(31) |
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#define USBPCR_AVLD_REG BIT(30) |
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#define USBPCR_COMMONONN BIT(25) |
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#define USBPCR_VBUSVLDEXT BIT(24) |
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#define USBPCR_VBUSVLDEXTSEL BIT(23) |
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#define USBPCR_POR BIT(22) |
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#define USBPCR_SIDDQ BIT(21) |
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#define USBPCR_OTG_DISABLE BIT(20) |
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#define USBPCR_TXPREEMPHTUNE BIT(6) |
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#define USBPCR_IDPULLUP_MASK GENMASK(29, 28) |
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#define USBPCR_IDPULLUP_ALWAYS 0x2 |
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#define USBPCR_IDPULLUP_SUSPEND 0x1 |
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#define USBPCR_IDPULLUP_OTG 0x0 |
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#define USBPCR_COMPDISTUNE_MASK GENMASK(19, 17) |
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#define USBPCR_COMPDISTUNE_DFT 0x4 |
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#define USBPCR_OTGTUNE_MASK GENMASK(16, 14) |
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#define USBPCR_OTGTUNE_DFT 0x4 |
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#define USBPCR_SQRXTUNE_MASK GENMASK(13, 11) |
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#define USBPCR_SQRXTUNE_DCR_20PCT 0x7 |
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#define USBPCR_SQRXTUNE_DFT 0x3 |
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#define USBPCR_TXFSLSTUNE_MASK GENMASK(10, 7) |
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#define USBPCR_TXFSLSTUNE_DCR_50PPT 0xf |
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#define USBPCR_TXFSLSTUNE_DCR_25PPT 0x7 |
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#define USBPCR_TXFSLSTUNE_DFT 0x3 |
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#define USBPCR_TXFSLSTUNE_INC_25PPT 0x1 |
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#define USBPCR_TXFSLSTUNE_INC_50PPT 0x0 |
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#define USBPCR_TXHSXVTUNE_MASK GENMASK(5, 4) |
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#define USBPCR_TXHSXVTUNE_DFT 0x3 |
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#define USBPCR_TXHSXVTUNE_DCR_15MV 0x1 |
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#define USBPCR_TXRISETUNE_MASK GENMASK(5, 4) |
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#define USBPCR_TXRISETUNE_DFT 0x3 |
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#define USBPCR_TXVREFTUNE_MASK GENMASK(3, 0) |
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#define USBPCR_TXVREFTUNE_INC_75PPT 0xb |
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#define USBPCR_TXVREFTUNE_INC_25PPT 0x7 |
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#define USBPCR_TXVREFTUNE_DFT 0x5 |
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/* bits within the USBRDTR register */ |
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#define USBRDT_UTMI_RST BIT(27) |
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#define USBRDT_HB_MASK BIT(26) |
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#define USBRDT_VBFIL_LD_EN BIT(25) |
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#define USBRDT_IDDIG_EN BIT(24) |
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#define USBRDT_IDDIG_REG BIT(23) |
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#define USBRDT_VBFIL_EN BIT(2) |
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/* bits within the USBPCR1 register */ |
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#define USBPCR1_BVLD_REG BIT(31) |
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#define USBPCR1_DPPD BIT(29) |
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#define USBPCR1_DMPD BIT(28) |
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#define USBPCR1_USB_SEL BIT(28) |
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#define USBPCR1_PORT_RST BIT(21) |
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#define USBPCR1_WORD_IF_16BIT BIT(19) |
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struct ingenic_soc_info { |
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void (*usb_phy_init)(struct phy *phy); |
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}; |
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struct ingenic_usb_phy { |
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const struct ingenic_soc_info *soc_info; |
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struct phy *phy; |
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void __iomem *base; |
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struct clk *clk; |
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struct regulator *vcc_supply; |
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}; |
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static int ingenic_usb_phy_init(struct phy *phy) |
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{ |
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struct ingenic_usb_phy *priv = phy_get_drvdata(phy); |
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int err; |
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u32 reg; |
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err = clk_prepare_enable(priv->clk); |
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if (err) { |
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dev_err(&phy->dev, "Unable to start clock: %d\n", err); |
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return err; |
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} |
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priv->soc_info->usb_phy_init(phy); |
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/* Wait for PHY to reset */ |
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usleep_range(30, 300); |
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reg = readl(priv->base + REG_USBPCR_OFFSET); |
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writel(reg & ~USBPCR_POR, priv->base + REG_USBPCR_OFFSET); |
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usleep_range(300, 1000); |
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return 0; |
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} |
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static int ingenic_usb_phy_exit(struct phy *phy) |
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{ |
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struct ingenic_usb_phy *priv = phy_get_drvdata(phy); |
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clk_disable_unprepare(priv->clk); |
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regulator_disable(priv->vcc_supply); |
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return 0; |
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} |
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static int ingenic_usb_phy_power_on(struct phy *phy) |
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{ |
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struct ingenic_usb_phy *priv = phy_get_drvdata(phy); |
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int err; |
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err = regulator_enable(priv->vcc_supply); |
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if (err) { |
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dev_err(&phy->dev, "Unable to enable VCC: %d\n", err); |
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return err; |
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} |
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return 0; |
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} |
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static int ingenic_usb_phy_power_off(struct phy *phy) |
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{ |
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struct ingenic_usb_phy *priv = phy_get_drvdata(phy); |
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regulator_disable(priv->vcc_supply); |
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return 0; |
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} |
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static int ingenic_usb_phy_set_mode(struct phy *phy, |
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enum phy_mode mode, int submode) |
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{ |
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struct ingenic_usb_phy *priv = phy_get_drvdata(phy); |
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u32 reg; |
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switch (mode) { |
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case PHY_MODE_USB_HOST: |
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reg = readl(priv->base + REG_USBPCR_OFFSET); |
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u32p_replace_bits(®, 1, USBPCR_USB_MODE); |
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u32p_replace_bits(®, 0, USBPCR_VBUSVLDEXT); |
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u32p_replace_bits(®, 0, USBPCR_VBUSVLDEXTSEL); |
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u32p_replace_bits(®, 0, USBPCR_OTG_DISABLE); |
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writel(reg, priv->base + REG_USBPCR_OFFSET); |
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break; |
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case PHY_MODE_USB_DEVICE: |
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reg = readl(priv->base + REG_USBPCR_OFFSET); |
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u32p_replace_bits(®, 0, USBPCR_USB_MODE); |
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u32p_replace_bits(®, 1, USBPCR_VBUSVLDEXT); |
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u32p_replace_bits(®, 1, USBPCR_VBUSVLDEXTSEL); |
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u32p_replace_bits(®, 1, USBPCR_OTG_DISABLE); |
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writel(reg, priv->base + REG_USBPCR_OFFSET); |
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break; |
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case PHY_MODE_USB_OTG: |
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reg = readl(priv->base + REG_USBPCR_OFFSET); |
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u32p_replace_bits(®, 1, USBPCR_USB_MODE); |
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u32p_replace_bits(®, 1, USBPCR_VBUSVLDEXT); |
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u32p_replace_bits(®, 1, USBPCR_VBUSVLDEXTSEL); |
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u32p_replace_bits(®, 0, USBPCR_OTG_DISABLE); |
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writel(reg, priv->base + REG_USBPCR_OFFSET); |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static const struct phy_ops ingenic_usb_phy_ops = { |
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.init = ingenic_usb_phy_init, |
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.exit = ingenic_usb_phy_exit, |
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.power_on = ingenic_usb_phy_power_on, |
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.power_off = ingenic_usb_phy_power_off, |
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.set_mode = ingenic_usb_phy_set_mode, |
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.owner = THIS_MODULE, |
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}; |
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static void jz4770_usb_phy_init(struct phy *phy) |
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{ |
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struct ingenic_usb_phy *priv = phy_get_drvdata(phy); |
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u32 reg; |
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reg = USBPCR_AVLD_REG | USBPCR_COMMONONN | USBPCR_POR | |
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FIELD_PREP(USBPCR_IDPULLUP_MASK, USBPCR_IDPULLUP_ALWAYS) | |
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FIELD_PREP(USBPCR_COMPDISTUNE_MASK, USBPCR_COMPDISTUNE_DFT) | |
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FIELD_PREP(USBPCR_OTGTUNE_MASK, USBPCR_OTGTUNE_DFT) | |
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FIELD_PREP(USBPCR_SQRXTUNE_MASK, USBPCR_SQRXTUNE_DFT) | |
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FIELD_PREP(USBPCR_TXFSLSTUNE_MASK, USBPCR_TXFSLSTUNE_DFT) | |
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FIELD_PREP(USBPCR_TXRISETUNE_MASK, USBPCR_TXRISETUNE_DFT) | |
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FIELD_PREP(USBPCR_TXVREFTUNE_MASK, USBPCR_TXVREFTUNE_DFT); |
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writel(reg, priv->base + REG_USBPCR_OFFSET); |
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} |
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static void jz4775_usb_phy_init(struct phy *phy) |
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{ |
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struct ingenic_usb_phy *priv = phy_get_drvdata(phy); |
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u32 reg; |
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reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_USB_SEL | |
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USBPCR1_WORD_IF_16BIT; |
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writel(reg, priv->base + REG_USBPCR1_OFFSET); |
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reg = USBPCR_COMMONONN | USBPCR_POR | |
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FIELD_PREP(USBPCR_TXVREFTUNE_MASK, USBPCR_TXVREFTUNE_INC_75PPT); |
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writel(reg, priv->base + REG_USBPCR_OFFSET); |
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} |
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static void jz4780_usb_phy_init(struct phy *phy) |
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{ |
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struct ingenic_usb_phy *priv = phy_get_drvdata(phy); |
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u32 reg; |
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reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_USB_SEL | |
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USBPCR1_WORD_IF_16BIT; |
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writel(reg, priv->base + REG_USBPCR1_OFFSET); |
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reg = USBPCR_TXPREEMPHTUNE | USBPCR_COMMONONN | USBPCR_POR; |
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writel(reg, priv->base + REG_USBPCR_OFFSET); |
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} |
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static void x1000_usb_phy_init(struct phy *phy) |
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{ |
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struct ingenic_usb_phy *priv = phy_get_drvdata(phy); |
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u32 reg; |
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reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_WORD_IF_16BIT; |
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writel(reg, priv->base + REG_USBPCR1_OFFSET); |
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reg = USBPCR_TXPREEMPHTUNE | USBPCR_COMMONONN | USBPCR_POR | |
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FIELD_PREP(USBPCR_SQRXTUNE_MASK, USBPCR_SQRXTUNE_DCR_20PCT) | |
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FIELD_PREP(USBPCR_TXHSXVTUNE_MASK, USBPCR_TXHSXVTUNE_DCR_15MV) | |
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FIELD_PREP(USBPCR_TXVREFTUNE_MASK, USBPCR_TXVREFTUNE_INC_25PPT); |
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writel(reg, priv->base + REG_USBPCR_OFFSET); |
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} |
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static void x1830_usb_phy_init(struct phy *phy) |
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{ |
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struct ingenic_usb_phy *priv = phy_get_drvdata(phy); |
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u32 reg; |
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/* rdt */ |
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writel(USBRDT_VBFIL_EN | USBRDT_UTMI_RST, priv->base + REG_USBRDT_OFFSET); |
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reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_WORD_IF_16BIT | |
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USBPCR1_DMPD | USBPCR1_DPPD; |
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writel(reg, priv->base + REG_USBPCR1_OFFSET); |
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reg = USBPCR_VBUSVLDEXT | USBPCR_TXPREEMPHTUNE | USBPCR_COMMONONN | USBPCR_POR | |
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FIELD_PREP(USBPCR_IDPULLUP_MASK, USBPCR_IDPULLUP_OTG); |
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writel(reg, priv->base + REG_USBPCR_OFFSET); |
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} |
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static void x2000_usb_phy_init(struct phy *phy) |
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{ |
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struct ingenic_usb_phy *priv = phy_get_drvdata(phy); |
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u32 reg; |
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reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_DPPD | USBPCR1_DMPD; |
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writel(reg & ~USBPCR1_PORT_RST, priv->base + REG_USBPCR1_OFFSET); |
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reg = USBPCR_POR | FIELD_PREP(USBPCR_IDPULLUP_MASK, USBPCR_IDPULLUP_OTG); |
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writel(reg, priv->base + REG_USBPCR_OFFSET); |
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} |
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static const struct ingenic_soc_info jz4770_soc_info = { |
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.usb_phy_init = jz4770_usb_phy_init, |
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}; |
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static const struct ingenic_soc_info jz4775_soc_info = { |
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.usb_phy_init = jz4775_usb_phy_init, |
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}; |
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static const struct ingenic_soc_info jz4780_soc_info = { |
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.usb_phy_init = jz4780_usb_phy_init, |
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}; |
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static const struct ingenic_soc_info x1000_soc_info = { |
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.usb_phy_init = x1000_usb_phy_init, |
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}; |
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static const struct ingenic_soc_info x1830_soc_info = { |
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.usb_phy_init = x1830_usb_phy_init, |
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}; |
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static const struct ingenic_soc_info x2000_soc_info = { |
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.usb_phy_init = x2000_usb_phy_init, |
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}; |
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static int ingenic_usb_phy_probe(struct platform_device *pdev) |
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{ |
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struct ingenic_usb_phy *priv; |
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struct phy_provider *provider; |
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struct device *dev = &pdev->dev; |
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int err; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->soc_info = device_get_match_data(dev); |
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if (!priv->soc_info) { |
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dev_err(dev, "Error: No device match found\n"); |
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return -ENODEV; |
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} |
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priv->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(priv->base)) { |
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dev_err(dev, "Failed to map registers\n"); |
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return PTR_ERR(priv->base); |
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} |
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priv->clk = devm_clk_get(dev, NULL); |
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if (IS_ERR(priv->clk)) { |
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err = PTR_ERR(priv->clk); |
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if (err != -EPROBE_DEFER) |
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dev_err(dev, "Failed to get clock\n"); |
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return err; |
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} |
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priv->vcc_supply = devm_regulator_get(dev, "vcc"); |
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if (IS_ERR(priv->vcc_supply)) { |
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err = PTR_ERR(priv->vcc_supply); |
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if (err != -EPROBE_DEFER) |
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dev_err(dev, "Failed to get regulator\n"); |
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return err; |
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} |
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priv->phy = devm_phy_create(dev, NULL, &ingenic_usb_phy_ops); |
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if (IS_ERR(priv->phy)) |
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return PTR_ERR(priv->phy); |
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phy_set_drvdata(priv->phy, priv); |
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provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
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return PTR_ERR_OR_ZERO(provider); |
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} |
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static const struct of_device_id ingenic_usb_phy_of_matches[] = { |
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{ .compatible = "ingenic,jz4770-phy", .data = &jz4770_soc_info }, |
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{ .compatible = "ingenic,jz4775-phy", .data = &jz4775_soc_info }, |
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{ .compatible = "ingenic,jz4780-phy", .data = &jz4780_soc_info }, |
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{ .compatible = "ingenic,x1000-phy", .data = &x1000_soc_info }, |
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{ .compatible = "ingenic,x1830-phy", .data = &x1830_soc_info }, |
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{ .compatible = "ingenic,x2000-phy", .data = &x2000_soc_info }, |
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{ /* sentinel */ } |
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}; |
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MODULE_DEVICE_TABLE(of, ingenic_usb_phy_of_matches); |
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static struct platform_driver ingenic_usb_phy_driver = { |
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.probe = ingenic_usb_phy_probe, |
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.driver = { |
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.name = "ingenic-usb-phy", |
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.of_match_table = ingenic_usb_phy_of_matches, |
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}, |
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}; |
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module_platform_driver(ingenic_usb_phy_driver); |
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MODULE_AUTHOR("周琰杰 (Zhou Yanjie) <[email protected]>"); |
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MODULE_AUTHOR("漆鹏振 (Qi Pengzhen) <[email protected]>"); |
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MODULE_AUTHOR("Paul Cercueil <[email protected]>"); |
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MODULE_DESCRIPTION("Ingenic SoCs USB PHY driver"); |
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MODULE_LICENSE("GPL");
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