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463 lines
11 KiB
463 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Amlogic G12A USB3 + PCIE Combo PHY driver |
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* |
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* Copyright (C) 2017 Amlogic, Inc. All rights reserved |
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* Copyright (C) 2019 BayLibre, SAS |
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* Author: Neil Armstrong <[email protected]> |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/bitops.h> |
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#include <linux/clk.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/phy/phy.h> |
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#include <linux/regmap.h> |
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#include <linux/reset.h> |
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#include <linux/platform_device.h> |
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#include <dt-bindings/phy/phy.h> |
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#define PHY_R0 0x00 |
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#define PHY_R0_PCIE_POWER_STATE GENMASK(4, 0) |
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#define PHY_R0_PCIE_USB3_SWITCH GENMASK(6, 5) |
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#define PHY_R1 0x04 |
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#define PHY_R1_PHY_TX1_TERM_OFFSET GENMASK(4, 0) |
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#define PHY_R1_PHY_TX0_TERM_OFFSET GENMASK(9, 5) |
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#define PHY_R1_PHY_RX1_EQ GENMASK(12, 10) |
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#define PHY_R1_PHY_RX0_EQ GENMASK(15, 13) |
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#define PHY_R1_PHY_LOS_LEVEL GENMASK(20, 16) |
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#define PHY_R1_PHY_LOS_BIAS GENMASK(23, 21) |
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#define PHY_R1_PHY_REF_CLKDIV2 BIT(24) |
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#define PHY_R1_PHY_MPLL_MULTIPLIER GENMASK(31, 25) |
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#define PHY_R2 0x08 |
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#define PHY_R2_PCS_TX_DEEMPH_GEN2_6DB GENMASK(5, 0) |
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#define PHY_R2_PCS_TX_DEEMPH_GEN2_3P5DB GENMASK(11, 6) |
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#define PHY_R2_PCS_TX_DEEMPH_GEN1 GENMASK(17, 12) |
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#define PHY_R2_PHY_TX_VBOOST_LVL GENMASK(20, 18) |
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#define PHY_R4 0x10 |
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#define PHY_R4_PHY_CR_WRITE BIT(0) |
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#define PHY_R4_PHY_CR_READ BIT(1) |
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#define PHY_R4_PHY_CR_DATA_IN GENMASK(17, 2) |
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#define PHY_R4_PHY_CR_CAP_DATA BIT(18) |
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#define PHY_R4_PHY_CR_CAP_ADDR BIT(19) |
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#define PHY_R5 0x14 |
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#define PHY_R5_PHY_CR_DATA_OUT GENMASK(15, 0) |
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#define PHY_R5_PHY_CR_ACK BIT(16) |
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#define PHY_R5_PHY_BS_OUT BIT(17) |
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#define PCIE_RESET_DELAY 500 |
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struct phy_g12a_usb3_pcie_priv { |
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struct regmap *regmap; |
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struct regmap *regmap_cr; |
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struct clk *clk_ref; |
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struct reset_control *reset; |
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struct phy *phy; |
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unsigned int mode; |
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}; |
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static const struct regmap_config phy_g12a_usb3_pcie_regmap_conf = { |
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.reg_bits = 8, |
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.val_bits = 32, |
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.reg_stride = 4, |
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.max_register = PHY_R5, |
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}; |
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static int phy_g12a_usb3_pcie_cr_bus_addr(struct phy_g12a_usb3_pcie_priv *priv, |
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unsigned int addr) |
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{ |
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unsigned int val, reg; |
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int ret; |
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reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, addr); |
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regmap_write(priv->regmap, PHY_R4, reg); |
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regmap_write(priv->regmap, PHY_R4, reg); |
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regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_ADDR); |
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ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, |
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(val & PHY_R5_PHY_CR_ACK), |
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5, 1000); |
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if (ret) |
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return ret; |
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regmap_write(priv->regmap, PHY_R4, reg); |
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ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, |
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!(val & PHY_R5_PHY_CR_ACK), |
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5, 1000); |
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if (ret) |
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return ret; |
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return 0; |
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} |
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static int phy_g12a_usb3_pcie_cr_bus_read(void *context, unsigned int addr, |
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unsigned int *data) |
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{ |
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struct phy_g12a_usb3_pcie_priv *priv = context; |
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unsigned int val; |
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int ret; |
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ret = phy_g12a_usb3_pcie_cr_bus_addr(priv, addr); |
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if (ret) |
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return ret; |
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regmap_write(priv->regmap, PHY_R4, 0); |
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regmap_write(priv->regmap, PHY_R4, PHY_R4_PHY_CR_READ); |
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ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, |
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(val & PHY_R5_PHY_CR_ACK), |
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5, 1000); |
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if (ret) |
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return ret; |
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*data = FIELD_GET(PHY_R5_PHY_CR_DATA_OUT, val); |
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regmap_write(priv->regmap, PHY_R4, 0); |
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ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, |
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!(val & PHY_R5_PHY_CR_ACK), |
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5, 1000); |
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if (ret) |
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return ret; |
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return 0; |
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} |
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static int phy_g12a_usb3_pcie_cr_bus_write(void *context, unsigned int addr, |
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unsigned int data) |
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{ |
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struct phy_g12a_usb3_pcie_priv *priv = context; |
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unsigned int val, reg; |
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int ret; |
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ret = phy_g12a_usb3_pcie_cr_bus_addr(priv, addr); |
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if (ret) |
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return ret; |
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reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, data); |
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regmap_write(priv->regmap, PHY_R4, reg); |
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regmap_write(priv->regmap, PHY_R4, reg); |
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regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_DATA); |
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ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, |
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(val & PHY_R5_PHY_CR_ACK), |
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5, 1000); |
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if (ret) |
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return ret; |
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regmap_write(priv->regmap, PHY_R4, reg); |
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ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, |
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(val & PHY_R5_PHY_CR_ACK) == 0, |
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5, 1000); |
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if (ret) |
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return ret; |
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regmap_write(priv->regmap, PHY_R4, reg); |
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regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_WRITE); |
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ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, |
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(val & PHY_R5_PHY_CR_ACK), |
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5, 1000); |
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if (ret) |
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return ret; |
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regmap_write(priv->regmap, PHY_R4, reg); |
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ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, |
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(val & PHY_R5_PHY_CR_ACK) == 0, |
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5, 1000); |
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if (ret) |
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return ret; |
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return 0; |
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} |
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static const struct regmap_config phy_g12a_usb3_pcie_cr_regmap_conf = { |
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.reg_bits = 16, |
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.val_bits = 16, |
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.reg_read = phy_g12a_usb3_pcie_cr_bus_read, |
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.reg_write = phy_g12a_usb3_pcie_cr_bus_write, |
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.max_register = 0xffff, |
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.disable_locking = true, |
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}; |
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static int phy_g12a_usb3_init(struct phy *phy) |
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{ |
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struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy); |
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int data, ret; |
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ret = reset_control_reset(priv->reset); |
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if (ret) |
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return ret; |
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/* Switch PHY to USB3 */ |
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/* TODO figure out how to handle when PCIe was set in the bootloader */ |
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regmap_update_bits(priv->regmap, PHY_R0, |
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PHY_R0_PCIE_USB3_SWITCH, |
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PHY_R0_PCIE_USB3_SWITCH); |
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/* |
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* WORKAROUND: There is SSPHY suspend bug due to |
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* which USB enumerates |
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* in HS mode instead of SS mode. Workaround it by asserting |
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* LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus |
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* mode |
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*/ |
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ret = regmap_update_bits(priv->regmap_cr, 0x102d, BIT(7), BIT(7)); |
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if (ret) |
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return ret; |
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ret = regmap_update_bits(priv->regmap_cr, 0x1010, 0xff0, 20); |
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if (ret) |
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return ret; |
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/* |
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* Fix RX Equalization setting as follows |
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* LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0 |
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* LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1 |
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* LANE0.RX_OVRD_IN_HI.RX_EQ set to 3 |
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* LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1 |
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*/ |
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ret = regmap_read(priv->regmap_cr, 0x1006, &data); |
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if (ret) |
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return ret; |
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data &= ~BIT(6); |
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data |= BIT(7); |
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data &= ~(0x7 << 8); |
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data |= (0x3 << 8); |
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data |= (1 << 11); |
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ret = regmap_write(priv->regmap_cr, 0x1006, data); |
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if (ret) |
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return ret; |
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/* |
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* Set EQ and TX launch amplitudes as follows |
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* LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22 |
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* LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127 |
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* LANE0.TX_OVRD_DRV_LO.EN set to 1. |
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*/ |
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ret = regmap_read(priv->regmap_cr, 0x1002, &data); |
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if (ret) |
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return ret; |
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data &= ~0x3f80; |
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data |= (0x16 << 7); |
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data &= ~0x7f; |
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data |= (0x7f | BIT(14)); |
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ret = regmap_write(priv->regmap_cr, 0x1002, data); |
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if (ret) |
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return ret; |
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/* MPLL_LOOP_CTL.PROP_CNTRL = 8 */ |
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ret = regmap_update_bits(priv->regmap_cr, 0x30, 0xf << 4, 8 << 4); |
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if (ret) |
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return ret; |
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regmap_update_bits(priv->regmap, PHY_R2, |
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PHY_R2_PHY_TX_VBOOST_LVL, |
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FIELD_PREP(PHY_R2_PHY_TX_VBOOST_LVL, 0x4)); |
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regmap_update_bits(priv->regmap, PHY_R1, |
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PHY_R1_PHY_LOS_BIAS | PHY_R1_PHY_LOS_LEVEL, |
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FIELD_PREP(PHY_R1_PHY_LOS_BIAS, 4) | |
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FIELD_PREP(PHY_R1_PHY_LOS_LEVEL, 9)); |
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return 0; |
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} |
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static int phy_g12a_usb3_pcie_power_on(struct phy *phy) |
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{ |
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struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy); |
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if (priv->mode == PHY_TYPE_USB3) |
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return 0; |
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regmap_update_bits(priv->regmap, PHY_R0, |
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PHY_R0_PCIE_POWER_STATE, |
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FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c)); |
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return 0; |
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} |
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static int phy_g12a_usb3_pcie_power_off(struct phy *phy) |
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{ |
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struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy); |
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if (priv->mode == PHY_TYPE_USB3) |
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return 0; |
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regmap_update_bits(priv->regmap, PHY_R0, |
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PHY_R0_PCIE_POWER_STATE, |
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FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1d)); |
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return 0; |
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} |
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static int phy_g12a_usb3_pcie_reset(struct phy *phy) |
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{ |
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struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy); |
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int ret; |
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if (priv->mode == PHY_TYPE_USB3) |
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return 0; |
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ret = reset_control_assert(priv->reset); |
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if (ret) |
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return ret; |
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udelay(PCIE_RESET_DELAY); |
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ret = reset_control_deassert(priv->reset); |
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if (ret) |
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return ret; |
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udelay(PCIE_RESET_DELAY); |
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return 0; |
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} |
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static int phy_g12a_usb3_pcie_init(struct phy *phy) |
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{ |
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struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy); |
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if (priv->mode == PHY_TYPE_USB3) |
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return phy_g12a_usb3_init(phy); |
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return 0; |
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} |
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static int phy_g12a_usb3_pcie_exit(struct phy *phy) |
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{ |
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struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy); |
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if (priv->mode == PHY_TYPE_USB3) |
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return reset_control_reset(priv->reset); |
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return 0; |
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} |
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static struct phy *phy_g12a_usb3_pcie_xlate(struct device *dev, |
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struct of_phandle_args *args) |
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{ |
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struct phy_g12a_usb3_pcie_priv *priv = dev_get_drvdata(dev); |
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unsigned int mode; |
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if (args->args_count < 1) { |
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dev_err(dev, "invalid number of arguments\n"); |
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return ERR_PTR(-EINVAL); |
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} |
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mode = args->args[0]; |
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if (mode != PHY_TYPE_USB3 && mode != PHY_TYPE_PCIE) { |
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dev_err(dev, "invalid phy mode select argument\n"); |
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return ERR_PTR(-EINVAL); |
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} |
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priv->mode = mode; |
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return priv->phy; |
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} |
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static const struct phy_ops phy_g12a_usb3_pcie_ops = { |
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.init = phy_g12a_usb3_pcie_init, |
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.exit = phy_g12a_usb3_pcie_exit, |
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.power_on = phy_g12a_usb3_pcie_power_on, |
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.power_off = phy_g12a_usb3_pcie_power_off, |
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.reset = phy_g12a_usb3_pcie_reset, |
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.owner = THIS_MODULE, |
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}; |
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static int phy_g12a_usb3_pcie_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct device_node *np = dev->of_node; |
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struct phy_g12a_usb3_pcie_priv *priv; |
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struct phy_provider *phy_provider; |
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void __iomem *base; |
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int ret; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(base)) |
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return PTR_ERR(base); |
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priv->regmap = devm_regmap_init_mmio(dev, base, |
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&phy_g12a_usb3_pcie_regmap_conf); |
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if (IS_ERR(priv->regmap)) |
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return PTR_ERR(priv->regmap); |
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priv->regmap_cr = devm_regmap_init(dev, NULL, priv, |
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&phy_g12a_usb3_pcie_cr_regmap_conf); |
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if (IS_ERR(priv->regmap_cr)) |
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return PTR_ERR(priv->regmap_cr); |
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priv->clk_ref = devm_clk_get(dev, "ref_clk"); |
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if (IS_ERR(priv->clk_ref)) |
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return PTR_ERR(priv->clk_ref); |
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ret = clk_prepare_enable(priv->clk_ref); |
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if (ret) |
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goto err_disable_clk_ref; |
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priv->reset = devm_reset_control_array_get_exclusive(dev); |
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if (IS_ERR(priv->reset)) |
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return PTR_ERR(priv->reset); |
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priv->phy = devm_phy_create(dev, np, &phy_g12a_usb3_pcie_ops); |
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if (IS_ERR(priv->phy)) { |
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ret = PTR_ERR(priv->phy); |
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if (ret != -EPROBE_DEFER) |
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dev_err(dev, "failed to create PHY\n"); |
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return ret; |
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} |
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phy_set_drvdata(priv->phy, priv); |
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dev_set_drvdata(dev, priv); |
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phy_provider = devm_of_phy_provider_register(dev, |
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phy_g12a_usb3_pcie_xlate); |
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return PTR_ERR_OR_ZERO(phy_provider); |
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err_disable_clk_ref: |
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clk_disable_unprepare(priv->clk_ref); |
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return ret; |
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} |
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static const struct of_device_id phy_g12a_usb3_pcie_of_match[] = { |
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{ .compatible = "amlogic,g12a-usb3-pcie-phy", }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, phy_g12a_usb3_pcie_of_match); |
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static struct platform_driver phy_g12a_usb3_pcie_driver = { |
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.probe = phy_g12a_usb3_pcie_probe, |
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.driver = { |
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.name = "phy-g12a-usb3-pcie", |
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.of_match_table = phy_g12a_usb3_pcie_of_match, |
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}, |
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}; |
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module_platform_driver(phy_g12a_usb3_pcie_driver); |
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MODULE_AUTHOR("Neil Armstrong <[email protected]>"); |
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MODULE_DESCRIPTION("Amlogic G12A USB3 + PCIE Combo PHY driver"); |
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MODULE_LICENSE("GPL v2");
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