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1034 lines
26 KiB
1034 lines
26 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* PCIe driver for Renesas R-Car SoCs |
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* Copyright (C) 2014-2020 Renesas Electronics Europe Ltd |
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* |
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* Based on: |
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* arch/sh/drivers/pci/pcie-sh7786.c |
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* arch/sh/drivers/pci/ops-sh7786.c |
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* Copyright (C) 2009 - 2011 Paul Mundt |
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* |
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* Author: Phil Edworthy <[email protected]> |
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*/ |
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|
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#include <linux/bitops.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/irqdomain.h> |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/msi.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_pci.h> |
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#include <linux/of_platform.h> |
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#include <linux/pci.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/slab.h> |
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|
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#include "pcie-rcar.h" |
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|
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struct rcar_msi { |
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DECLARE_BITMAP(used, INT_PCI_MSI_NR); |
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struct irq_domain *domain; |
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struct mutex map_lock; |
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spinlock_t mask_lock; |
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int irq1; |
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int irq2; |
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}; |
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|
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/* Structure representing the PCIe interface */ |
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struct rcar_pcie_host { |
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struct rcar_pcie pcie; |
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struct phy *phy; |
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struct clk *bus_clk; |
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struct rcar_msi msi; |
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int (*phy_init_fn)(struct rcar_pcie_host *host); |
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}; |
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|
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static struct rcar_pcie_host *msi_to_host(struct rcar_msi *msi) |
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{ |
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return container_of(msi, struct rcar_pcie_host, msi); |
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} |
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|
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static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) |
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{ |
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unsigned int shift = BITS_PER_BYTE * (where & 3); |
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u32 val = rcar_pci_read_reg(pcie, where & ~3); |
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|
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return val >> shift; |
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} |
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|
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/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ |
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static int rcar_pcie_config_access(struct rcar_pcie_host *host, |
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unsigned char access_type, struct pci_bus *bus, |
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unsigned int devfn, int where, u32 *data) |
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{ |
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struct rcar_pcie *pcie = &host->pcie; |
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unsigned int dev, func, reg, index; |
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|
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dev = PCI_SLOT(devfn); |
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func = PCI_FUNC(devfn); |
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reg = where & ~3; |
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index = reg / 4; |
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|
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/* |
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* While each channel has its own memory-mapped extended config |
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* space, it's generally only accessible when in endpoint mode. |
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* When in root complex mode, the controller is unable to target |
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* itself with either type 0 or type 1 accesses, and indeed, any |
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* controller initiated target transfer to its own config space |
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* result in a completer abort. |
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* |
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* Each channel effectively only supports a single device, but as |
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* the same channel <-> device access works for any PCI_SLOT() |
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* value, we cheat a bit here and bind the controller's config |
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* space to devfn 0 in order to enable self-enumeration. In this |
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* case the regular ECAR/ECDR path is sidelined and the mangled |
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* config access itself is initiated as an internal bus transaction. |
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*/ |
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if (pci_is_root_bus(bus)) { |
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if (dev != 0) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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|
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if (access_type == RCAR_PCI_ACCESS_READ) |
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*data = rcar_pci_read_reg(pcie, PCICONF(index)); |
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else |
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rcar_pci_write_reg(pcie, *data, PCICONF(index)); |
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|
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return PCIBIOS_SUCCESSFUL; |
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} |
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|
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/* Clear errors */ |
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rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR); |
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|
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/* Set the PIO address */ |
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rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | |
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PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR); |
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|
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/* Enable the configuration access */ |
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if (pci_is_root_bus(bus->parent)) |
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rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR); |
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else |
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rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR); |
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|
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/* Check for errors */ |
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if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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|
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/* Check for master and target aborts */ |
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if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) & |
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(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT)) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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|
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if (access_type == RCAR_PCI_ACCESS_READ) |
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*data = rcar_pci_read_reg(pcie, PCIECDR); |
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else |
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rcar_pci_write_reg(pcie, *data, PCIECDR); |
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|
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/* Disable the configuration access */ |
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rcar_pci_write_reg(pcie, 0, PCIECCTLR); |
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|
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 *val) |
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{ |
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struct rcar_pcie_host *host = bus->sysdata; |
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int ret; |
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|
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ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ, |
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bus, devfn, where, val); |
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if (ret != PCIBIOS_SUCCESSFUL) { |
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*val = 0xffffffff; |
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return ret; |
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} |
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|
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if (size == 1) |
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*val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff; |
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else if (size == 2) |
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*val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff; |
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|
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dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", |
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bus->number, devfn, where, size, *val); |
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|
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return ret; |
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} |
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/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ |
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static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 val) |
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{ |
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struct rcar_pcie_host *host = bus->sysdata; |
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unsigned int shift; |
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u32 data; |
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int ret; |
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ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ, |
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bus, devfn, where, &data); |
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if (ret != PCIBIOS_SUCCESSFUL) |
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return ret; |
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dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", |
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bus->number, devfn, where, size, val); |
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if (size == 1) { |
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shift = BITS_PER_BYTE * (where & 3); |
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data &= ~(0xff << shift); |
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data |= ((val & 0xff) << shift); |
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} else if (size == 2) { |
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shift = BITS_PER_BYTE * (where & 2); |
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data &= ~(0xffff << shift); |
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data |= ((val & 0xffff) << shift); |
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} else |
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data = val; |
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ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_WRITE, |
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bus, devfn, where, &data); |
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return ret; |
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} |
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static struct pci_ops rcar_pcie_ops = { |
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.read = rcar_pcie_read_conf, |
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.write = rcar_pcie_write_conf, |
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}; |
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static void rcar_pcie_force_speedup(struct rcar_pcie *pcie) |
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{ |
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struct device *dev = pcie->dev; |
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unsigned int timeout = 1000; |
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u32 macsr; |
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if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS) |
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return; |
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if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) { |
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dev_err(dev, "Speed change already in progress\n"); |
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return; |
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} |
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macsr = rcar_pci_read_reg(pcie, MACSR); |
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if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS) |
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goto done; |
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|
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/* Set target link speed to 5.0 GT/s */ |
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rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS, |
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PCI_EXP_LNKSTA_CLS_5_0GB); |
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|
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/* Set speed change reason as intentional factor */ |
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rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0); |
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|
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/* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */ |
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if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL)) |
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rcar_pci_write_reg(pcie, macsr, MACSR); |
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|
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/* Start link speed change */ |
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rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE); |
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while (timeout--) { |
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macsr = rcar_pci_read_reg(pcie, MACSR); |
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if (macsr & SPCHGFIN) { |
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/* Clear the interrupt bits */ |
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rcar_pci_write_reg(pcie, macsr, MACSR); |
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if (macsr & SPCHGFAIL) |
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dev_err(dev, "Speed change failed\n"); |
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goto done; |
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} |
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msleep(1); |
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} |
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dev_err(dev, "Speed change timed out\n"); |
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done: |
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dev_info(dev, "Current link speed is %s GT/s\n", |
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(macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5"); |
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} |
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static void rcar_pcie_hw_enable(struct rcar_pcie_host *host) |
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{ |
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struct rcar_pcie *pcie = &host->pcie; |
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struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); |
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struct resource_entry *win; |
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LIST_HEAD(res); |
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int i = 0; |
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|
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/* Try setting 5 GT/s link speed */ |
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rcar_pcie_force_speedup(pcie); |
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|
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/* Setup PCI resources */ |
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resource_list_for_each_entry(win, &bridge->windows) { |
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struct resource *res = win->res; |
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if (!res->flags) |
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continue; |
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switch (resource_type(res)) { |
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case IORESOURCE_IO: |
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case IORESOURCE_MEM: |
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rcar_pcie_set_outbound(pcie, i, win); |
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i++; |
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break; |
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} |
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} |
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} |
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static int rcar_pcie_enable(struct rcar_pcie_host *host) |
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{ |
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struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); |
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rcar_pcie_hw_enable(host); |
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pci_add_flags(PCI_REASSIGN_ALL_BUS); |
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bridge->sysdata = host; |
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bridge->ops = &rcar_pcie_ops; |
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return pci_host_probe(bridge); |
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} |
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static int phy_wait_for_ack(struct rcar_pcie *pcie) |
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{ |
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struct device *dev = pcie->dev; |
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unsigned int timeout = 100; |
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while (timeout--) { |
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if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK) |
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return 0; |
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udelay(100); |
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} |
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dev_err(dev, "Access to PCIe phy timed out\n"); |
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return -ETIMEDOUT; |
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} |
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static void phy_write_reg(struct rcar_pcie *pcie, |
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unsigned int rate, u32 addr, |
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unsigned int lane, u32 data) |
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{ |
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u32 phyaddr; |
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phyaddr = WRITE_CMD | |
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((rate & 1) << RATE_POS) | |
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((lane & 0xf) << LANE_POS) | |
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((addr & 0xff) << ADR_POS); |
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/* Set write data */ |
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rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR); |
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rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR); |
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/* Ignore errors as they will be dealt with if the data link is down */ |
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phy_wait_for_ack(pcie); |
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/* Clear command */ |
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rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR); |
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rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR); |
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|
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/* Ignore errors as they will be dealt with if the data link is down */ |
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phy_wait_for_ack(pcie); |
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} |
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static int rcar_pcie_hw_init(struct rcar_pcie *pcie) |
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{ |
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int err; |
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|
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/* Begin initialization */ |
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rcar_pci_write_reg(pcie, 0, PCIETCTLR); |
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|
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/* Set mode */ |
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rcar_pci_write_reg(pcie, 1, PCIEMSR); |
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err = rcar_pcie_wait_for_phyrdy(pcie); |
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if (err) |
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return err; |
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/* |
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* Initial header for port config space is type 1, set the device |
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* class to match. Hardware takes care of propagating the IDSETR |
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* settings, so there is no need to bother with a quirk. |
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*/ |
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rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1); |
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|
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/* |
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* Setup Secondary Bus Number & Subordinate Bus Number, even though |
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* they aren't used, to avoid bridge being detected as broken. |
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*/ |
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rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1); |
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rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1); |
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|
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/* Initialize default capabilities. */ |
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rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); |
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rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), |
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PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4); |
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rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f, |
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PCI_HEADER_TYPE_BRIDGE); |
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|
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/* Enable data link layer active state reporting */ |
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rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC, |
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PCI_EXP_LNKCAP_DLLLARC); |
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|
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/* Write out the physical slot number = 0 */ |
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rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0); |
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|
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/* Set the completion timer timeout to the maximum 50ms. */ |
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rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50); |
|
|
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/* Terminate list of capabilities (Next Capability Offset=0) */ |
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rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0); |
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|
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/* Enable MSI */ |
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if (IS_ENABLED(CONFIG_PCI_MSI)) |
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rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); |
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|
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rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); |
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|
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/* Finish initialization - establish a PCI Express link */ |
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rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); |
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|
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/* This will timeout if we don't have a link. */ |
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err = rcar_pcie_wait_for_dl(pcie); |
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if (err) |
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return err; |
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|
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/* Enable INTx interrupts */ |
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rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8); |
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|
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wmb(); |
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|
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return 0; |
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} |
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static int rcar_pcie_phy_init_h1(struct rcar_pcie_host *host) |
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{ |
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struct rcar_pcie *pcie = &host->pcie; |
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|
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/* Initialize the phy */ |
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phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191); |
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phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180); |
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phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188); |
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phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188); |
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phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014); |
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phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014); |
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phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0); |
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phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB); |
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phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062); |
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phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000); |
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phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000); |
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phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806); |
|
|
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phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5); |
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phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F); |
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phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000); |
|
|
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return 0; |
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} |
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|
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static int rcar_pcie_phy_init_gen2(struct rcar_pcie_host *host) |
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{ |
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struct rcar_pcie *pcie = &host->pcie; |
|
|
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/* |
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* These settings come from the R-Car Series, 2nd Generation User's |
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* Manual, section 50.3.1 (2) Initialization of the physical layer. |
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*/ |
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rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR); |
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rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA); |
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rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); |
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rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); |
|
|
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rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR); |
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/* The following value is for DC connection, no termination resistor */ |
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rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA); |
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rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); |
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rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); |
|
|
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return 0; |
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} |
|
|
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static int rcar_pcie_phy_init_gen3(struct rcar_pcie_host *host) |
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{ |
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int err; |
|
|
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err = phy_init(host->phy); |
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if (err) |
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return err; |
|
|
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err = phy_power_on(host->phy); |
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if (err) |
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phy_exit(host->phy); |
|
|
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return err; |
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} |
|
|
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static irqreturn_t rcar_pcie_msi_irq(int irq, void *data) |
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{ |
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struct rcar_pcie_host *host = data; |
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struct rcar_pcie *pcie = &host->pcie; |
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struct rcar_msi *msi = &host->msi; |
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struct device *dev = pcie->dev; |
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unsigned long reg; |
|
|
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reg = rcar_pci_read_reg(pcie, PCIEMSIFR); |
|
|
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/* MSI & INTx share an interrupt - we only handle MSI here */ |
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if (!reg) |
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return IRQ_NONE; |
|
|
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while (reg) { |
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unsigned int index = find_first_bit(®, 32); |
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unsigned int msi_irq; |
|
|
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msi_irq = irq_find_mapping(msi->domain->parent, index); |
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if (msi_irq) { |
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generic_handle_irq(msi_irq); |
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} else { |
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/* Unknown MSI, just clear it */ |
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dev_dbg(dev, "unexpected MSI\n"); |
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rcar_pci_write_reg(pcie, BIT(index), PCIEMSIFR); |
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} |
|
|
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/* see if there's any more pending in this vector */ |
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reg = rcar_pci_read_reg(pcie, PCIEMSIFR); |
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} |
|
|
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return IRQ_HANDLED; |
|
} |
|
|
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static void rcar_msi_top_irq_ack(struct irq_data *d) |
|
{ |
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irq_chip_ack_parent(d); |
|
} |
|
|
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static void rcar_msi_top_irq_mask(struct irq_data *d) |
|
{ |
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pci_msi_mask_irq(d); |
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irq_chip_mask_parent(d); |
|
} |
|
|
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static void rcar_msi_top_irq_unmask(struct irq_data *d) |
|
{ |
|
pci_msi_unmask_irq(d); |
|
irq_chip_unmask_parent(d); |
|
} |
|
|
|
static struct irq_chip rcar_msi_top_chip = { |
|
.name = "PCIe MSI", |
|
.irq_ack = rcar_msi_top_irq_ack, |
|
.irq_mask = rcar_msi_top_irq_mask, |
|
.irq_unmask = rcar_msi_top_irq_unmask, |
|
}; |
|
|
|
static void rcar_msi_irq_ack(struct irq_data *d) |
|
{ |
|
struct rcar_msi *msi = irq_data_get_irq_chip_data(d); |
|
struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; |
|
|
|
/* clear the interrupt */ |
|
rcar_pci_write_reg(pcie, BIT(d->hwirq), PCIEMSIFR); |
|
} |
|
|
|
static void rcar_msi_irq_mask(struct irq_data *d) |
|
{ |
|
struct rcar_msi *msi = irq_data_get_irq_chip_data(d); |
|
struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; |
|
unsigned long flags; |
|
u32 value; |
|
|
|
spin_lock_irqsave(&msi->mask_lock, flags); |
|
value = rcar_pci_read_reg(pcie, PCIEMSIIER); |
|
value &= ~BIT(d->hwirq); |
|
rcar_pci_write_reg(pcie, value, PCIEMSIIER); |
|
spin_unlock_irqrestore(&msi->mask_lock, flags); |
|
} |
|
|
|
static void rcar_msi_irq_unmask(struct irq_data *d) |
|
{ |
|
struct rcar_msi *msi = irq_data_get_irq_chip_data(d); |
|
struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; |
|
unsigned long flags; |
|
u32 value; |
|
|
|
spin_lock_irqsave(&msi->mask_lock, flags); |
|
value = rcar_pci_read_reg(pcie, PCIEMSIIER); |
|
value |= BIT(d->hwirq); |
|
rcar_pci_write_reg(pcie, value, PCIEMSIIER); |
|
spin_unlock_irqrestore(&msi->mask_lock, flags); |
|
} |
|
|
|
static int rcar_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force) |
|
{ |
|
return -EINVAL; |
|
} |
|
|
|
static void rcar_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) |
|
{ |
|
struct rcar_msi *msi = irq_data_get_irq_chip_data(data); |
|
struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; |
|
|
|
msg->address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE; |
|
msg->address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR); |
|
msg->data = data->hwirq; |
|
} |
|
|
|
static struct irq_chip rcar_msi_bottom_chip = { |
|
.name = "Rcar MSI", |
|
.irq_ack = rcar_msi_irq_ack, |
|
.irq_mask = rcar_msi_irq_mask, |
|
.irq_unmask = rcar_msi_irq_unmask, |
|
.irq_set_affinity = rcar_msi_set_affinity, |
|
.irq_compose_msi_msg = rcar_compose_msi_msg, |
|
}; |
|
|
|
static int rcar_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, |
|
unsigned int nr_irqs, void *args) |
|
{ |
|
struct rcar_msi *msi = domain->host_data; |
|
unsigned int i; |
|
int hwirq; |
|
|
|
mutex_lock(&msi->map_lock); |
|
|
|
hwirq = bitmap_find_free_region(msi->used, INT_PCI_MSI_NR, order_base_2(nr_irqs)); |
|
|
|
mutex_unlock(&msi->map_lock); |
|
|
|
if (hwirq < 0) |
|
return -ENOSPC; |
|
|
|
for (i = 0; i < nr_irqs; i++) |
|
irq_domain_set_info(domain, virq + i, hwirq + i, |
|
&rcar_msi_bottom_chip, domain->host_data, |
|
handle_edge_irq, NULL, NULL); |
|
|
|
return 0; |
|
} |
|
|
|
static void rcar_msi_domain_free(struct irq_domain *domain, unsigned int virq, |
|
unsigned int nr_irqs) |
|
{ |
|
struct irq_data *d = irq_domain_get_irq_data(domain, virq); |
|
struct rcar_msi *msi = domain->host_data; |
|
|
|
mutex_lock(&msi->map_lock); |
|
|
|
bitmap_release_region(msi->used, d->hwirq, order_base_2(nr_irqs)); |
|
|
|
mutex_unlock(&msi->map_lock); |
|
} |
|
|
|
static const struct irq_domain_ops rcar_msi_domain_ops = { |
|
.alloc = rcar_msi_domain_alloc, |
|
.free = rcar_msi_domain_free, |
|
}; |
|
|
|
static struct msi_domain_info rcar_msi_info = { |
|
.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | |
|
MSI_FLAG_MULTI_PCI_MSI), |
|
.chip = &rcar_msi_top_chip, |
|
}; |
|
|
|
static int rcar_allocate_domains(struct rcar_msi *msi) |
|
{ |
|
struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; |
|
struct fwnode_handle *fwnode = dev_fwnode(pcie->dev); |
|
struct irq_domain *parent; |
|
|
|
parent = irq_domain_create_linear(fwnode, INT_PCI_MSI_NR, |
|
&rcar_msi_domain_ops, msi); |
|
if (!parent) { |
|
dev_err(pcie->dev, "failed to create IRQ domain\n"); |
|
return -ENOMEM; |
|
} |
|
irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS); |
|
|
|
msi->domain = pci_msi_create_irq_domain(fwnode, &rcar_msi_info, parent); |
|
if (!msi->domain) { |
|
dev_err(pcie->dev, "failed to create MSI domain\n"); |
|
irq_domain_remove(parent); |
|
return -ENOMEM; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static void rcar_free_domains(struct rcar_msi *msi) |
|
{ |
|
struct irq_domain *parent = msi->domain->parent; |
|
|
|
irq_domain_remove(msi->domain); |
|
irq_domain_remove(parent); |
|
} |
|
|
|
static int rcar_pcie_enable_msi(struct rcar_pcie_host *host) |
|
{ |
|
struct rcar_pcie *pcie = &host->pcie; |
|
struct device *dev = pcie->dev; |
|
struct rcar_msi *msi = &host->msi; |
|
struct resource res; |
|
int err; |
|
|
|
mutex_init(&msi->map_lock); |
|
spin_lock_init(&msi->mask_lock); |
|
|
|
err = of_address_to_resource(dev->of_node, 0, &res); |
|
if (err) |
|
return err; |
|
|
|
err = rcar_allocate_domains(msi); |
|
if (err) |
|
return err; |
|
|
|
/* Two irqs are for MSI, but they are also used for non-MSI irqs */ |
|
err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq, |
|
IRQF_SHARED | IRQF_NO_THREAD, |
|
rcar_msi_bottom_chip.name, host); |
|
if (err < 0) { |
|
dev_err(dev, "failed to request IRQ: %d\n", err); |
|
goto err; |
|
} |
|
|
|
err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq, |
|
IRQF_SHARED | IRQF_NO_THREAD, |
|
rcar_msi_bottom_chip.name, host); |
|
if (err < 0) { |
|
dev_err(dev, "failed to request IRQ: %d\n", err); |
|
goto err; |
|
} |
|
|
|
/* disable all MSIs */ |
|
rcar_pci_write_reg(pcie, 0, PCIEMSIIER); |
|
|
|
/* |
|
* Setup MSI data target using RC base address address, which |
|
* is guaranteed to be in the low 32bit range on any RCar HW. |
|
*/ |
|
rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); |
|
rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); |
|
|
|
return 0; |
|
|
|
err: |
|
rcar_free_domains(msi); |
|
return err; |
|
} |
|
|
|
static void rcar_pcie_teardown_msi(struct rcar_pcie_host *host) |
|
{ |
|
struct rcar_pcie *pcie = &host->pcie; |
|
|
|
/* Disable all MSI interrupts */ |
|
rcar_pci_write_reg(pcie, 0, PCIEMSIIER); |
|
|
|
/* Disable address decoding of the MSI interrupt, MSIFE */ |
|
rcar_pci_write_reg(pcie, 0, PCIEMSIALR); |
|
|
|
rcar_free_domains(&host->msi); |
|
} |
|
|
|
static int rcar_pcie_get_resources(struct rcar_pcie_host *host) |
|
{ |
|
struct rcar_pcie *pcie = &host->pcie; |
|
struct device *dev = pcie->dev; |
|
struct resource res; |
|
int err, i; |
|
|
|
host->phy = devm_phy_optional_get(dev, "pcie"); |
|
if (IS_ERR(host->phy)) |
|
return PTR_ERR(host->phy); |
|
|
|
err = of_address_to_resource(dev->of_node, 0, &res); |
|
if (err) |
|
return err; |
|
|
|
pcie->base = devm_ioremap_resource(dev, &res); |
|
if (IS_ERR(pcie->base)) |
|
return PTR_ERR(pcie->base); |
|
|
|
host->bus_clk = devm_clk_get(dev, "pcie_bus"); |
|
if (IS_ERR(host->bus_clk)) { |
|
dev_err(dev, "cannot get pcie bus clock\n"); |
|
return PTR_ERR(host->bus_clk); |
|
} |
|
|
|
i = irq_of_parse_and_map(dev->of_node, 0); |
|
if (!i) { |
|
dev_err(dev, "cannot get platform resources for msi interrupt\n"); |
|
err = -ENOENT; |
|
goto err_irq1; |
|
} |
|
host->msi.irq1 = i; |
|
|
|
i = irq_of_parse_and_map(dev->of_node, 1); |
|
if (!i) { |
|
dev_err(dev, "cannot get platform resources for msi interrupt\n"); |
|
err = -ENOENT; |
|
goto err_irq2; |
|
} |
|
host->msi.irq2 = i; |
|
|
|
return 0; |
|
|
|
err_irq2: |
|
irq_dispose_mapping(host->msi.irq1); |
|
err_irq1: |
|
return err; |
|
} |
|
|
|
static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie, |
|
struct resource_entry *entry, |
|
int *index) |
|
{ |
|
u64 restype = entry->res->flags; |
|
u64 cpu_addr = entry->res->start; |
|
u64 cpu_end = entry->res->end; |
|
u64 pci_addr = entry->res->start - entry->offset; |
|
u32 flags = LAM_64BIT | LAR_ENABLE; |
|
u64 mask; |
|
u64 size = resource_size(entry->res); |
|
int idx = *index; |
|
|
|
if (restype & IORESOURCE_PREFETCH) |
|
flags |= LAM_PREFETCH; |
|
|
|
while (cpu_addr < cpu_end) { |
|
if (idx >= MAX_NR_INBOUND_MAPS - 1) { |
|
dev_err(pcie->dev, "Failed to map inbound regions!\n"); |
|
return -EINVAL; |
|
} |
|
/* |
|
* If the size of the range is larger than the alignment of |
|
* the start address, we have to use multiple entries to |
|
* perform the mapping. |
|
*/ |
|
if (cpu_addr > 0) { |
|
unsigned long nr_zeros = __ffs64(cpu_addr); |
|
u64 alignment = 1ULL << nr_zeros; |
|
|
|
size = min(size, alignment); |
|
} |
|
/* Hardware supports max 4GiB inbound region */ |
|
size = min(size, 1ULL << 32); |
|
|
|
mask = roundup_pow_of_two(size) - 1; |
|
mask &= ~0xf; |
|
|
|
rcar_pcie_set_inbound(pcie, cpu_addr, pci_addr, |
|
lower_32_bits(mask) | flags, idx, true); |
|
|
|
pci_addr += size; |
|
cpu_addr += size; |
|
idx += 2; |
|
} |
|
*index = idx; |
|
|
|
return 0; |
|
} |
|
|
|
static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie_host *host) |
|
{ |
|
struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); |
|
struct resource_entry *entry; |
|
int index = 0, err = 0; |
|
|
|
resource_list_for_each_entry(entry, &bridge->dma_ranges) { |
|
err = rcar_pcie_inbound_ranges(&host->pcie, entry, &index); |
|
if (err) |
|
break; |
|
} |
|
|
|
return err; |
|
} |
|
|
|
static const struct of_device_id rcar_pcie_of_match[] = { |
|
{ .compatible = "renesas,pcie-r8a7779", |
|
.data = rcar_pcie_phy_init_h1 }, |
|
{ .compatible = "renesas,pcie-r8a7790", |
|
.data = rcar_pcie_phy_init_gen2 }, |
|
{ .compatible = "renesas,pcie-r8a7791", |
|
.data = rcar_pcie_phy_init_gen2 }, |
|
{ .compatible = "renesas,pcie-rcar-gen2", |
|
.data = rcar_pcie_phy_init_gen2 }, |
|
{ .compatible = "renesas,pcie-r8a7795", |
|
.data = rcar_pcie_phy_init_gen3 }, |
|
{ .compatible = "renesas,pcie-rcar-gen3", |
|
.data = rcar_pcie_phy_init_gen3 }, |
|
{}, |
|
}; |
|
|
|
static int rcar_pcie_probe(struct platform_device *pdev) |
|
{ |
|
struct device *dev = &pdev->dev; |
|
struct rcar_pcie_host *host; |
|
struct rcar_pcie *pcie; |
|
u32 data; |
|
int err; |
|
struct pci_host_bridge *bridge; |
|
|
|
bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host)); |
|
if (!bridge) |
|
return -ENOMEM; |
|
|
|
host = pci_host_bridge_priv(bridge); |
|
pcie = &host->pcie; |
|
pcie->dev = dev; |
|
platform_set_drvdata(pdev, host); |
|
|
|
pm_runtime_enable(pcie->dev); |
|
err = pm_runtime_get_sync(pcie->dev); |
|
if (err < 0) { |
|
dev_err(pcie->dev, "pm_runtime_get_sync failed\n"); |
|
goto err_pm_put; |
|
} |
|
|
|
err = rcar_pcie_get_resources(host); |
|
if (err < 0) { |
|
dev_err(dev, "failed to request resources: %d\n", err); |
|
goto err_pm_put; |
|
} |
|
|
|
err = clk_prepare_enable(host->bus_clk); |
|
if (err) { |
|
dev_err(dev, "failed to enable bus clock: %d\n", err); |
|
goto err_unmap_msi_irqs; |
|
} |
|
|
|
err = rcar_pcie_parse_map_dma_ranges(host); |
|
if (err) |
|
goto err_clk_disable; |
|
|
|
host->phy_init_fn = of_device_get_match_data(dev); |
|
err = host->phy_init_fn(host); |
|
if (err) { |
|
dev_err(dev, "failed to init PCIe PHY\n"); |
|
goto err_clk_disable; |
|
} |
|
|
|
/* Failure to get a link might just be that no cards are inserted */ |
|
if (rcar_pcie_hw_init(pcie)) { |
|
dev_info(dev, "PCIe link down\n"); |
|
err = -ENODEV; |
|
goto err_phy_shutdown; |
|
} |
|
|
|
data = rcar_pci_read_reg(pcie, MACSR); |
|
dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); |
|
|
|
if (IS_ENABLED(CONFIG_PCI_MSI)) { |
|
err = rcar_pcie_enable_msi(host); |
|
if (err < 0) { |
|
dev_err(dev, |
|
"failed to enable MSI support: %d\n", |
|
err); |
|
goto err_phy_shutdown; |
|
} |
|
} |
|
|
|
err = rcar_pcie_enable(host); |
|
if (err) |
|
goto err_msi_teardown; |
|
|
|
return 0; |
|
|
|
err_msi_teardown: |
|
if (IS_ENABLED(CONFIG_PCI_MSI)) |
|
rcar_pcie_teardown_msi(host); |
|
|
|
err_phy_shutdown: |
|
if (host->phy) { |
|
phy_power_off(host->phy); |
|
phy_exit(host->phy); |
|
} |
|
|
|
err_clk_disable: |
|
clk_disable_unprepare(host->bus_clk); |
|
|
|
err_unmap_msi_irqs: |
|
irq_dispose_mapping(host->msi.irq2); |
|
irq_dispose_mapping(host->msi.irq1); |
|
|
|
err_pm_put: |
|
pm_runtime_put(dev); |
|
pm_runtime_disable(dev); |
|
|
|
return err; |
|
} |
|
|
|
static int __maybe_unused rcar_pcie_resume(struct device *dev) |
|
{ |
|
struct rcar_pcie_host *host = dev_get_drvdata(dev); |
|
struct rcar_pcie *pcie = &host->pcie; |
|
unsigned int data; |
|
int err; |
|
|
|
err = rcar_pcie_parse_map_dma_ranges(host); |
|
if (err) |
|
return 0; |
|
|
|
/* Failure to get a link might just be that no cards are inserted */ |
|
err = host->phy_init_fn(host); |
|
if (err) { |
|
dev_info(dev, "PCIe link down\n"); |
|
return 0; |
|
} |
|
|
|
data = rcar_pci_read_reg(pcie, MACSR); |
|
dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); |
|
|
|
/* Enable MSI */ |
|
if (IS_ENABLED(CONFIG_PCI_MSI)) { |
|
struct resource res; |
|
u32 val; |
|
|
|
of_address_to_resource(dev->of_node, 0, &res); |
|
rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); |
|
rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); |
|
|
|
bitmap_to_arr32(&val, host->msi.used, INT_PCI_MSI_NR); |
|
rcar_pci_write_reg(pcie, val, PCIEMSIIER); |
|
} |
|
|
|
rcar_pcie_hw_enable(host); |
|
|
|
return 0; |
|
} |
|
|
|
static int rcar_pcie_resume_noirq(struct device *dev) |
|
{ |
|
struct rcar_pcie_host *host = dev_get_drvdata(dev); |
|
struct rcar_pcie *pcie = &host->pcie; |
|
|
|
if (rcar_pci_read_reg(pcie, PMSR) && |
|
!(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN)) |
|
return 0; |
|
|
|
/* Re-establish the PCIe link */ |
|
rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); |
|
rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); |
|
return rcar_pcie_wait_for_dl(pcie); |
|
} |
|
|
|
static const struct dev_pm_ops rcar_pcie_pm_ops = { |
|
SET_SYSTEM_SLEEP_PM_OPS(NULL, rcar_pcie_resume) |
|
.resume_noirq = rcar_pcie_resume_noirq, |
|
}; |
|
|
|
static struct platform_driver rcar_pcie_driver = { |
|
.driver = { |
|
.name = "rcar-pcie", |
|
.of_match_table = rcar_pcie_of_match, |
|
.pm = &rcar_pcie_pm_ops, |
|
.suppress_bind_attrs = true, |
|
}, |
|
.probe = rcar_pcie_probe, |
|
}; |
|
builtin_platform_driver(rcar_pcie_driver);
|
|
|