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1027 lines
26 KiB
1027 lines
26 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* MediaTek PCIe host controller driver. |
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* |
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* Copyright (c) 2020 MediaTek Inc. |
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* Author: Jianjun Wang <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/iopoll.h> |
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#include <linux/irq.h> |
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#include <linux/irqchip/chained_irq.h> |
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#include <linux/irqdomain.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/msi.h> |
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#include <linux/pci.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_domain.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/reset.h> |
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#include "../pci.h" |
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#define PCIE_SETTING_REG 0x80 |
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#define PCIE_PCI_IDS_1 0x9c |
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#define PCI_CLASS(class) (class << 8) |
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#define PCIE_RC_MODE BIT(0) |
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#define PCIE_CFGNUM_REG 0x140 |
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#define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0)) |
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#define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8)) |
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#define PCIE_CFG_BYTE_EN(bytes) (((bytes) << 16) & GENMASK(19, 16)) |
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#define PCIE_CFG_FORCE_BYTE_EN BIT(20) |
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#define PCIE_CFG_OFFSET_ADDR 0x1000 |
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#define PCIE_CFG_HEADER(bus, devfn) \ |
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(PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn)) |
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#define PCIE_RST_CTRL_REG 0x148 |
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#define PCIE_MAC_RSTB BIT(0) |
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#define PCIE_PHY_RSTB BIT(1) |
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#define PCIE_BRG_RSTB BIT(2) |
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#define PCIE_PE_RSTB BIT(3) |
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#define PCIE_LTSSM_STATUS_REG 0x150 |
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#define PCIE_LTSSM_STATE_MASK GENMASK(28, 24) |
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#define PCIE_LTSSM_STATE(val) ((val & PCIE_LTSSM_STATE_MASK) >> 24) |
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#define PCIE_LTSSM_STATE_L2_IDLE 0x14 |
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#define PCIE_LINK_STATUS_REG 0x154 |
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#define PCIE_PORT_LINKUP BIT(8) |
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#define PCIE_MSI_SET_NUM 8 |
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#define PCIE_MSI_IRQS_PER_SET 32 |
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#define PCIE_MSI_IRQS_NUM \ |
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(PCIE_MSI_IRQS_PER_SET * PCIE_MSI_SET_NUM) |
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#define PCIE_INT_ENABLE_REG 0x180 |
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#define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8) |
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#define PCIE_MSI_SHIFT 8 |
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#define PCIE_INTX_SHIFT 24 |
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#define PCIE_INTX_ENABLE \ |
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GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT) |
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#define PCIE_INT_STATUS_REG 0x184 |
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#define PCIE_MSI_SET_ENABLE_REG 0x190 |
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#define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0) |
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#define PCIE_MSI_SET_BASE_REG 0xc00 |
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#define PCIE_MSI_SET_OFFSET 0x10 |
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#define PCIE_MSI_SET_STATUS_OFFSET 0x04 |
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#define PCIE_MSI_SET_ENABLE_OFFSET 0x08 |
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#define PCIE_MSI_SET_ADDR_HI_BASE 0xc80 |
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#define PCIE_MSI_SET_ADDR_HI_OFFSET 0x04 |
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#define PCIE_ICMD_PM_REG 0x198 |
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#define PCIE_TURN_OFF_LINK BIT(4) |
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#define PCIE_TRANS_TABLE_BASE_REG 0x800 |
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#define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4 |
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#define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8 |
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#define PCIE_ATR_TRSL_ADDR_MSB_OFFSET 0xc |
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#define PCIE_ATR_TRSL_PARAM_OFFSET 0x10 |
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#define PCIE_ATR_TLB_SET_OFFSET 0x20 |
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#define PCIE_MAX_TRANS_TABLES 8 |
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#define PCIE_ATR_EN BIT(0) |
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#define PCIE_ATR_SIZE(size) \ |
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(((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN) |
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#define PCIE_ATR_ID(id) ((id) & GENMASK(3, 0)) |
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#define PCIE_ATR_TYPE_MEM PCIE_ATR_ID(0) |
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#define PCIE_ATR_TYPE_IO PCIE_ATR_ID(1) |
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#define PCIE_ATR_TLP_TYPE(type) (((type) << 16) & GENMASK(18, 16)) |
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#define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0) |
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#define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2) |
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/** |
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* struct mtk_msi_set - MSI information for each set |
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* @base: IO mapped register base |
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* @msg_addr: MSI message address |
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* @saved_irq_state: IRQ enable state saved at suspend time |
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*/ |
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struct mtk_msi_set { |
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void __iomem *base; |
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phys_addr_t msg_addr; |
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u32 saved_irq_state; |
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}; |
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/** |
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* struct mtk_pcie_port - PCIe port information |
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* @dev: pointer to PCIe device |
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* @base: IO mapped register base |
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* @reg_base: physical register base |
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* @mac_reset: MAC reset control |
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* @phy_reset: PHY reset control |
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* @phy: PHY controller block |
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* @clks: PCIe clocks |
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* @num_clks: PCIe clocks count for this port |
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* @irq: PCIe controller interrupt number |
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* @saved_irq_state: IRQ enable state saved at suspend time |
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* @irq_lock: lock protecting IRQ register access |
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* @intx_domain: legacy INTx IRQ domain |
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* @msi_domain: MSI IRQ domain |
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* @msi_bottom_domain: MSI IRQ bottom domain |
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* @msi_sets: MSI sets information |
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* @lock: lock protecting IRQ bit map |
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* @msi_irq_in_use: bit map for assigned MSI IRQ |
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*/ |
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struct mtk_pcie_port { |
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struct device *dev; |
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void __iomem *base; |
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phys_addr_t reg_base; |
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struct reset_control *mac_reset; |
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struct reset_control *phy_reset; |
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struct phy *phy; |
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struct clk_bulk_data *clks; |
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int num_clks; |
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int irq; |
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u32 saved_irq_state; |
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raw_spinlock_t irq_lock; |
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struct irq_domain *intx_domain; |
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struct irq_domain *msi_domain; |
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struct irq_domain *msi_bottom_domain; |
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struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM]; |
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struct mutex lock; |
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DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM); |
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}; |
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/** |
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* mtk_pcie_config_tlp_header() - Configure a configuration TLP header |
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* @bus: PCI bus to query |
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* @devfn: device/function number |
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* @where: offset in config space |
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* @size: data size in TLP header |
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* |
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* Set byte enable field and device information in configuration TLP header. |
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*/ |
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static void mtk_pcie_config_tlp_header(struct pci_bus *bus, unsigned int devfn, |
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int where, int size) |
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{ |
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struct mtk_pcie_port *port = bus->sysdata; |
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int bytes; |
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u32 val; |
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bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3); |
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val = PCIE_CFG_FORCE_BYTE_EN | PCIE_CFG_BYTE_EN(bytes) | |
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PCIE_CFG_HEADER(bus->number, devfn); |
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writel_relaxed(val, port->base + PCIE_CFGNUM_REG); |
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} |
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static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, |
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int where) |
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{ |
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struct mtk_pcie_port *port = bus->sysdata; |
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return port->base + PCIE_CFG_OFFSET_ADDR + where; |
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} |
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static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 *val) |
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{ |
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mtk_pcie_config_tlp_header(bus, devfn, where, size); |
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return pci_generic_config_read32(bus, devfn, where, size, val); |
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} |
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static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 val) |
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{ |
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mtk_pcie_config_tlp_header(bus, devfn, where, size); |
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if (size <= 2) |
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val <<= (where & 0x3) * 8; |
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return pci_generic_config_write32(bus, devfn, where, 4, val); |
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} |
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static struct pci_ops mtk_pcie_ops = { |
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.map_bus = mtk_pcie_map_bus, |
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.read = mtk_pcie_config_read, |
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.write = mtk_pcie_config_write, |
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}; |
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static int mtk_pcie_set_trans_table(struct mtk_pcie_port *port, |
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resource_size_t cpu_addr, |
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resource_size_t pci_addr, |
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resource_size_t size, |
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unsigned long type, int num) |
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{ |
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void __iomem *table; |
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u32 val; |
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if (num >= PCIE_MAX_TRANS_TABLES) { |
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dev_err(port->dev, "not enough translate table for addr: %#llx, limited to [%d]\n", |
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(unsigned long long)cpu_addr, PCIE_MAX_TRANS_TABLES); |
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return -ENODEV; |
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} |
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table = port->base + PCIE_TRANS_TABLE_BASE_REG + |
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num * PCIE_ATR_TLB_SET_OFFSET; |
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writel_relaxed(lower_32_bits(cpu_addr) | PCIE_ATR_SIZE(fls(size) - 1), |
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table); |
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writel_relaxed(upper_32_bits(cpu_addr), |
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table + PCIE_ATR_SRC_ADDR_MSB_OFFSET); |
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writel_relaxed(lower_32_bits(pci_addr), |
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table + PCIE_ATR_TRSL_ADDR_LSB_OFFSET); |
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writel_relaxed(upper_32_bits(pci_addr), |
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table + PCIE_ATR_TRSL_ADDR_MSB_OFFSET); |
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if (type == IORESOURCE_IO) |
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val = PCIE_ATR_TYPE_IO | PCIE_ATR_TLP_TYPE_IO; |
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else |
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val = PCIE_ATR_TYPE_MEM | PCIE_ATR_TLP_TYPE_MEM; |
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writel_relaxed(val, table + PCIE_ATR_TRSL_PARAM_OFFSET); |
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return 0; |
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} |
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static void mtk_pcie_enable_msi(struct mtk_pcie_port *port) |
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{ |
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int i; |
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u32 val; |
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for (i = 0; i < PCIE_MSI_SET_NUM; i++) { |
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struct mtk_msi_set *msi_set = &port->msi_sets[i]; |
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msi_set->base = port->base + PCIE_MSI_SET_BASE_REG + |
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i * PCIE_MSI_SET_OFFSET; |
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msi_set->msg_addr = port->reg_base + PCIE_MSI_SET_BASE_REG + |
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i * PCIE_MSI_SET_OFFSET; |
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/* Configure the MSI capture address */ |
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writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base); |
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writel_relaxed(upper_32_bits(msi_set->msg_addr), |
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port->base + PCIE_MSI_SET_ADDR_HI_BASE + |
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i * PCIE_MSI_SET_ADDR_HI_OFFSET); |
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} |
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val = readl_relaxed(port->base + PCIE_MSI_SET_ENABLE_REG); |
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val |= PCIE_MSI_SET_ENABLE; |
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writel_relaxed(val, port->base + PCIE_MSI_SET_ENABLE_REG); |
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val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG); |
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val |= PCIE_MSI_ENABLE; |
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writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); |
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} |
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static int mtk_pcie_startup_port(struct mtk_pcie_port *port) |
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{ |
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struct resource_entry *entry; |
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struct pci_host_bridge *host = pci_host_bridge_from_priv(port); |
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unsigned int table_index = 0; |
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int err; |
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u32 val; |
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/* Set as RC mode */ |
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val = readl_relaxed(port->base + PCIE_SETTING_REG); |
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val |= PCIE_RC_MODE; |
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writel_relaxed(val, port->base + PCIE_SETTING_REG); |
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/* Set class code */ |
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val = readl_relaxed(port->base + PCIE_PCI_IDS_1); |
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val &= ~GENMASK(31, 8); |
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val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8); |
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writel_relaxed(val, port->base + PCIE_PCI_IDS_1); |
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/* Mask all INTx interrupts */ |
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val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG); |
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val &= ~PCIE_INTX_ENABLE; |
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writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); |
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/* Assert all reset signals */ |
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val = readl_relaxed(port->base + PCIE_RST_CTRL_REG); |
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val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB; |
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writel_relaxed(val, port->base + PCIE_RST_CTRL_REG); |
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/* |
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* Described in PCIe CEM specification setctions 2.2 (PERST# Signal) |
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* and 2.2.1 (Initial Power-Up (G3 to S0)). |
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* The deassertion of PERST# should be delayed 100ms (TPVPERL) |
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* for the power and clock to become stable. |
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*/ |
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msleep(100); |
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/* De-assert reset signals */ |
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val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB); |
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writel_relaxed(val, port->base + PCIE_RST_CTRL_REG); |
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/* Check if the link is up or not */ |
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err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_REG, val, |
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!!(val & PCIE_PORT_LINKUP), 20, |
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PCI_PM_D3COLD_WAIT * USEC_PER_MSEC); |
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if (err) { |
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val = readl_relaxed(port->base + PCIE_LTSSM_STATUS_REG); |
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dev_err(port->dev, "PCIe link down, ltssm reg val: %#x\n", val); |
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return err; |
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} |
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mtk_pcie_enable_msi(port); |
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/* Set PCIe translation windows */ |
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resource_list_for_each_entry(entry, &host->windows) { |
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struct resource *res = entry->res; |
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unsigned long type = resource_type(res); |
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resource_size_t cpu_addr; |
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resource_size_t pci_addr; |
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resource_size_t size; |
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const char *range_type; |
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if (type == IORESOURCE_IO) { |
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cpu_addr = pci_pio_to_address(res->start); |
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range_type = "IO"; |
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} else if (type == IORESOURCE_MEM) { |
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cpu_addr = res->start; |
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range_type = "MEM"; |
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} else { |
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continue; |
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} |
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pci_addr = res->start - entry->offset; |
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size = resource_size(res); |
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err = mtk_pcie_set_trans_table(port, cpu_addr, pci_addr, size, |
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type, table_index); |
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if (err) |
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return err; |
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dev_dbg(port->dev, "set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n", |
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range_type, table_index, (unsigned long long)cpu_addr, |
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(unsigned long long)pci_addr, (unsigned long long)size); |
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table_index++; |
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} |
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return 0; |
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} |
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static int mtk_pcie_set_affinity(struct irq_data *data, |
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const struct cpumask *mask, bool force) |
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{ |
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return -EINVAL; |
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} |
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static void mtk_pcie_msi_irq_mask(struct irq_data *data) |
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{ |
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pci_msi_mask_irq(data); |
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irq_chip_mask_parent(data); |
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} |
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static void mtk_pcie_msi_irq_unmask(struct irq_data *data) |
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{ |
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pci_msi_unmask_irq(data); |
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irq_chip_unmask_parent(data); |
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} |
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static struct irq_chip mtk_msi_irq_chip = { |
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.irq_ack = irq_chip_ack_parent, |
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.irq_mask = mtk_pcie_msi_irq_mask, |
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.irq_unmask = mtk_pcie_msi_irq_unmask, |
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.name = "MSI", |
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}; |
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static struct msi_domain_info mtk_msi_domain_info = { |
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | |
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MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), |
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.chip = &mtk_msi_irq_chip, |
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}; |
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static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) |
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{ |
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struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data); |
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struct mtk_pcie_port *port = data->domain->host_data; |
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unsigned long hwirq; |
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hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET; |
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msg->address_hi = upper_32_bits(msi_set->msg_addr); |
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msg->address_lo = lower_32_bits(msi_set->msg_addr); |
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msg->data = hwirq; |
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dev_dbg(port->dev, "msi#%#lx address_hi %#x address_lo %#x data %d\n", |
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hwirq, msg->address_hi, msg->address_lo, msg->data); |
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} |
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static void mtk_msi_bottom_irq_ack(struct irq_data *data) |
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{ |
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struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data); |
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unsigned long hwirq; |
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hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET; |
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writel_relaxed(BIT(hwirq), msi_set->base + PCIE_MSI_SET_STATUS_OFFSET); |
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} |
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static void mtk_msi_bottom_irq_mask(struct irq_data *data) |
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{ |
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struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data); |
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struct mtk_pcie_port *port = data->domain->host_data; |
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unsigned long hwirq, flags; |
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u32 val; |
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hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET; |
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raw_spin_lock_irqsave(&port->irq_lock, flags); |
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val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); |
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val &= ~BIT(hwirq); |
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writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); |
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raw_spin_unlock_irqrestore(&port->irq_lock, flags); |
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} |
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static void mtk_msi_bottom_irq_unmask(struct irq_data *data) |
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{ |
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struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data); |
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struct mtk_pcie_port *port = data->domain->host_data; |
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unsigned long hwirq, flags; |
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u32 val; |
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hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET; |
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raw_spin_lock_irqsave(&port->irq_lock, flags); |
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val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); |
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val |= BIT(hwirq); |
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writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); |
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raw_spin_unlock_irqrestore(&port->irq_lock, flags); |
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} |
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static struct irq_chip mtk_msi_bottom_irq_chip = { |
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.irq_ack = mtk_msi_bottom_irq_ack, |
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.irq_mask = mtk_msi_bottom_irq_mask, |
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.irq_unmask = mtk_msi_bottom_irq_unmask, |
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.irq_compose_msi_msg = mtk_compose_msi_msg, |
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.irq_set_affinity = mtk_pcie_set_affinity, |
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.name = "MSI", |
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}; |
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static int mtk_msi_bottom_domain_alloc(struct irq_domain *domain, |
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unsigned int virq, unsigned int nr_irqs, |
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void *arg) |
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{ |
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struct mtk_pcie_port *port = domain->host_data; |
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struct mtk_msi_set *msi_set; |
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int i, hwirq, set_idx; |
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mutex_lock(&port->lock); |
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hwirq = bitmap_find_free_region(port->msi_irq_in_use, PCIE_MSI_IRQS_NUM, |
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order_base_2(nr_irqs)); |
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mutex_unlock(&port->lock); |
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if (hwirq < 0) |
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return -ENOSPC; |
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|
|
set_idx = hwirq / PCIE_MSI_IRQS_PER_SET; |
|
msi_set = &port->msi_sets[set_idx]; |
|
|
|
for (i = 0; i < nr_irqs; i++) |
|
irq_domain_set_info(domain, virq + i, hwirq + i, |
|
&mtk_msi_bottom_irq_chip, msi_set, |
|
handle_edge_irq, NULL, NULL); |
|
|
|
return 0; |
|
} |
|
|
|
static void mtk_msi_bottom_domain_free(struct irq_domain *domain, |
|
unsigned int virq, unsigned int nr_irqs) |
|
{ |
|
struct mtk_pcie_port *port = domain->host_data; |
|
struct irq_data *data = irq_domain_get_irq_data(domain, virq); |
|
|
|
mutex_lock(&port->lock); |
|
|
|
bitmap_release_region(port->msi_irq_in_use, data->hwirq, |
|
order_base_2(nr_irqs)); |
|
|
|
mutex_unlock(&port->lock); |
|
|
|
irq_domain_free_irqs_common(domain, virq, nr_irqs); |
|
} |
|
|
|
static const struct irq_domain_ops mtk_msi_bottom_domain_ops = { |
|
.alloc = mtk_msi_bottom_domain_alloc, |
|
.free = mtk_msi_bottom_domain_free, |
|
}; |
|
|
|
static void mtk_intx_mask(struct irq_data *data) |
|
{ |
|
struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); |
|
unsigned long flags; |
|
u32 val; |
|
|
|
raw_spin_lock_irqsave(&port->irq_lock, flags); |
|
val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG); |
|
val &= ~BIT(data->hwirq + PCIE_INTX_SHIFT); |
|
writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); |
|
raw_spin_unlock_irqrestore(&port->irq_lock, flags); |
|
} |
|
|
|
static void mtk_intx_unmask(struct irq_data *data) |
|
{ |
|
struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); |
|
unsigned long flags; |
|
u32 val; |
|
|
|
raw_spin_lock_irqsave(&port->irq_lock, flags); |
|
val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG); |
|
val |= BIT(data->hwirq + PCIE_INTX_SHIFT); |
|
writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); |
|
raw_spin_unlock_irqrestore(&port->irq_lock, flags); |
|
} |
|
|
|
/** |
|
* mtk_intx_eoi() - Clear INTx IRQ status at the end of interrupt |
|
* @data: pointer to chip specific data |
|
* |
|
* As an emulated level IRQ, its interrupt status will remain |
|
* until the corresponding de-assert message is received; hence that |
|
* the status can only be cleared when the interrupt has been serviced. |
|
*/ |
|
static void mtk_intx_eoi(struct irq_data *data) |
|
{ |
|
struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); |
|
unsigned long hwirq; |
|
|
|
hwirq = data->hwirq + PCIE_INTX_SHIFT; |
|
writel_relaxed(BIT(hwirq), port->base + PCIE_INT_STATUS_REG); |
|
} |
|
|
|
static struct irq_chip mtk_intx_irq_chip = { |
|
.irq_mask = mtk_intx_mask, |
|
.irq_unmask = mtk_intx_unmask, |
|
.irq_eoi = mtk_intx_eoi, |
|
.irq_set_affinity = mtk_pcie_set_affinity, |
|
.name = "INTx", |
|
}; |
|
|
|
static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq, |
|
irq_hw_number_t hwirq) |
|
{ |
|
irq_set_chip_data(irq, domain->host_data); |
|
irq_set_chip_and_handler_name(irq, &mtk_intx_irq_chip, |
|
handle_fasteoi_irq, "INTx"); |
|
return 0; |
|
} |
|
|
|
static const struct irq_domain_ops intx_domain_ops = { |
|
.map = mtk_pcie_intx_map, |
|
}; |
|
|
|
static int mtk_pcie_init_irq_domains(struct mtk_pcie_port *port) |
|
{ |
|
struct device *dev = port->dev; |
|
struct device_node *intc_node, *node = dev->of_node; |
|
int ret; |
|
|
|
raw_spin_lock_init(&port->irq_lock); |
|
|
|
/* Setup INTx */ |
|
intc_node = of_get_child_by_name(node, "interrupt-controller"); |
|
if (!intc_node) { |
|
dev_err(dev, "missing interrupt-controller node\n"); |
|
return -ENODEV; |
|
} |
|
|
|
port->intx_domain = irq_domain_add_linear(intc_node, PCI_NUM_INTX, |
|
&intx_domain_ops, port); |
|
if (!port->intx_domain) { |
|
dev_err(dev, "failed to create INTx IRQ domain\n"); |
|
return -ENODEV; |
|
} |
|
|
|
/* Setup MSI */ |
|
mutex_init(&port->lock); |
|
|
|
port->msi_bottom_domain = irq_domain_add_linear(node, PCIE_MSI_IRQS_NUM, |
|
&mtk_msi_bottom_domain_ops, port); |
|
if (!port->msi_bottom_domain) { |
|
dev_err(dev, "failed to create MSI bottom domain\n"); |
|
ret = -ENODEV; |
|
goto err_msi_bottom_domain; |
|
} |
|
|
|
port->msi_domain = pci_msi_create_irq_domain(dev->fwnode, |
|
&mtk_msi_domain_info, |
|
port->msi_bottom_domain); |
|
if (!port->msi_domain) { |
|
dev_err(dev, "failed to create MSI domain\n"); |
|
ret = -ENODEV; |
|
goto err_msi_domain; |
|
} |
|
|
|
return 0; |
|
|
|
err_msi_domain: |
|
irq_domain_remove(port->msi_bottom_domain); |
|
err_msi_bottom_domain: |
|
irq_domain_remove(port->intx_domain); |
|
|
|
return ret; |
|
} |
|
|
|
static void mtk_pcie_irq_teardown(struct mtk_pcie_port *port) |
|
{ |
|
irq_set_chained_handler_and_data(port->irq, NULL, NULL); |
|
|
|
if (port->intx_domain) |
|
irq_domain_remove(port->intx_domain); |
|
|
|
if (port->msi_domain) |
|
irq_domain_remove(port->msi_domain); |
|
|
|
if (port->msi_bottom_domain) |
|
irq_domain_remove(port->msi_bottom_domain); |
|
|
|
irq_dispose_mapping(port->irq); |
|
} |
|
|
|
static void mtk_pcie_msi_handler(struct mtk_pcie_port *port, int set_idx) |
|
{ |
|
struct mtk_msi_set *msi_set = &port->msi_sets[set_idx]; |
|
unsigned long msi_enable, msi_status; |
|
unsigned int virq; |
|
irq_hw_number_t bit, hwirq; |
|
|
|
msi_enable = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); |
|
|
|
do { |
|
msi_status = readl_relaxed(msi_set->base + |
|
PCIE_MSI_SET_STATUS_OFFSET); |
|
msi_status &= msi_enable; |
|
if (!msi_status) |
|
break; |
|
|
|
for_each_set_bit(bit, &msi_status, PCIE_MSI_IRQS_PER_SET) { |
|
hwirq = bit + set_idx * PCIE_MSI_IRQS_PER_SET; |
|
virq = irq_find_mapping(port->msi_bottom_domain, hwirq); |
|
generic_handle_irq(virq); |
|
} |
|
} while (true); |
|
} |
|
|
|
static void mtk_pcie_irq_handler(struct irq_desc *desc) |
|
{ |
|
struct mtk_pcie_port *port = irq_desc_get_handler_data(desc); |
|
struct irq_chip *irqchip = irq_desc_get_chip(desc); |
|
unsigned long status; |
|
unsigned int virq; |
|
irq_hw_number_t irq_bit = PCIE_INTX_SHIFT; |
|
|
|
chained_irq_enter(irqchip, desc); |
|
|
|
status = readl_relaxed(port->base + PCIE_INT_STATUS_REG); |
|
for_each_set_bit_from(irq_bit, &status, PCI_NUM_INTX + |
|
PCIE_INTX_SHIFT) { |
|
virq = irq_find_mapping(port->intx_domain, |
|
irq_bit - PCIE_INTX_SHIFT); |
|
generic_handle_irq(virq); |
|
} |
|
|
|
irq_bit = PCIE_MSI_SHIFT; |
|
for_each_set_bit_from(irq_bit, &status, PCIE_MSI_SET_NUM + |
|
PCIE_MSI_SHIFT) { |
|
mtk_pcie_msi_handler(port, irq_bit - PCIE_MSI_SHIFT); |
|
|
|
writel_relaxed(BIT(irq_bit), port->base + PCIE_INT_STATUS_REG); |
|
} |
|
|
|
chained_irq_exit(irqchip, desc); |
|
} |
|
|
|
static int mtk_pcie_setup_irq(struct mtk_pcie_port *port) |
|
{ |
|
struct device *dev = port->dev; |
|
struct platform_device *pdev = to_platform_device(dev); |
|
int err; |
|
|
|
err = mtk_pcie_init_irq_domains(port); |
|
if (err) |
|
return err; |
|
|
|
port->irq = platform_get_irq(pdev, 0); |
|
if (port->irq < 0) |
|
return port->irq; |
|
|
|
irq_set_chained_handler_and_data(port->irq, mtk_pcie_irq_handler, port); |
|
|
|
return 0; |
|
} |
|
|
|
static int mtk_pcie_parse_port(struct mtk_pcie_port *port) |
|
{ |
|
struct device *dev = port->dev; |
|
struct platform_device *pdev = to_platform_device(dev); |
|
struct resource *regs; |
|
int ret; |
|
|
|
regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac"); |
|
if (!regs) |
|
return -EINVAL; |
|
port->base = devm_ioremap_resource(dev, regs); |
|
if (IS_ERR(port->base)) { |
|
dev_err(dev, "failed to map register base\n"); |
|
return PTR_ERR(port->base); |
|
} |
|
|
|
port->reg_base = regs->start; |
|
|
|
port->phy_reset = devm_reset_control_get_optional_exclusive(dev, "phy"); |
|
if (IS_ERR(port->phy_reset)) { |
|
ret = PTR_ERR(port->phy_reset); |
|
if (ret != -EPROBE_DEFER) |
|
dev_err(dev, "failed to get PHY reset\n"); |
|
|
|
return ret; |
|
} |
|
|
|
port->mac_reset = devm_reset_control_get_optional_exclusive(dev, "mac"); |
|
if (IS_ERR(port->mac_reset)) { |
|
ret = PTR_ERR(port->mac_reset); |
|
if (ret != -EPROBE_DEFER) |
|
dev_err(dev, "failed to get MAC reset\n"); |
|
|
|
return ret; |
|
} |
|
|
|
port->phy = devm_phy_optional_get(dev, "pcie-phy"); |
|
if (IS_ERR(port->phy)) { |
|
ret = PTR_ERR(port->phy); |
|
if (ret != -EPROBE_DEFER) |
|
dev_err(dev, "failed to get PHY\n"); |
|
|
|
return ret; |
|
} |
|
|
|
port->num_clks = devm_clk_bulk_get_all(dev, &port->clks); |
|
if (port->num_clks < 0) { |
|
dev_err(dev, "failed to get clocks\n"); |
|
return port->num_clks; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int mtk_pcie_power_up(struct mtk_pcie_port *port) |
|
{ |
|
struct device *dev = port->dev; |
|
int err; |
|
|
|
/* PHY power on and enable pipe clock */ |
|
reset_control_deassert(port->phy_reset); |
|
|
|
err = phy_init(port->phy); |
|
if (err) { |
|
dev_err(dev, "failed to initialize PHY\n"); |
|
goto err_phy_init; |
|
} |
|
|
|
err = phy_power_on(port->phy); |
|
if (err) { |
|
dev_err(dev, "failed to power on PHY\n"); |
|
goto err_phy_on; |
|
} |
|
|
|
/* MAC power on and enable transaction layer clocks */ |
|
reset_control_deassert(port->mac_reset); |
|
|
|
pm_runtime_enable(dev); |
|
pm_runtime_get_sync(dev); |
|
|
|
err = clk_bulk_prepare_enable(port->num_clks, port->clks); |
|
if (err) { |
|
dev_err(dev, "failed to enable clocks\n"); |
|
goto err_clk_init; |
|
} |
|
|
|
return 0; |
|
|
|
err_clk_init: |
|
pm_runtime_put_sync(dev); |
|
pm_runtime_disable(dev); |
|
reset_control_assert(port->mac_reset); |
|
phy_power_off(port->phy); |
|
err_phy_on: |
|
phy_exit(port->phy); |
|
err_phy_init: |
|
reset_control_assert(port->phy_reset); |
|
|
|
return err; |
|
} |
|
|
|
static void mtk_pcie_power_down(struct mtk_pcie_port *port) |
|
{ |
|
clk_bulk_disable_unprepare(port->num_clks, port->clks); |
|
|
|
pm_runtime_put_sync(port->dev); |
|
pm_runtime_disable(port->dev); |
|
reset_control_assert(port->mac_reset); |
|
|
|
phy_power_off(port->phy); |
|
phy_exit(port->phy); |
|
reset_control_assert(port->phy_reset); |
|
} |
|
|
|
static int mtk_pcie_setup(struct mtk_pcie_port *port) |
|
{ |
|
int err; |
|
|
|
err = mtk_pcie_parse_port(port); |
|
if (err) |
|
return err; |
|
|
|
/* Don't touch the hardware registers before power up */ |
|
err = mtk_pcie_power_up(port); |
|
if (err) |
|
return err; |
|
|
|
/* Try link up */ |
|
err = mtk_pcie_startup_port(port); |
|
if (err) |
|
goto err_setup; |
|
|
|
err = mtk_pcie_setup_irq(port); |
|
if (err) |
|
goto err_setup; |
|
|
|
return 0; |
|
|
|
err_setup: |
|
mtk_pcie_power_down(port); |
|
|
|
return err; |
|
} |
|
|
|
static int mtk_pcie_probe(struct platform_device *pdev) |
|
{ |
|
struct device *dev = &pdev->dev; |
|
struct mtk_pcie_port *port; |
|
struct pci_host_bridge *host; |
|
int err; |
|
|
|
host = devm_pci_alloc_host_bridge(dev, sizeof(*port)); |
|
if (!host) |
|
return -ENOMEM; |
|
|
|
port = pci_host_bridge_priv(host); |
|
|
|
port->dev = dev; |
|
platform_set_drvdata(pdev, port); |
|
|
|
err = mtk_pcie_setup(port); |
|
if (err) |
|
return err; |
|
|
|
host->ops = &mtk_pcie_ops; |
|
host->sysdata = port; |
|
|
|
err = pci_host_probe(host); |
|
if (err) { |
|
mtk_pcie_irq_teardown(port); |
|
mtk_pcie_power_down(port); |
|
return err; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int mtk_pcie_remove(struct platform_device *pdev) |
|
{ |
|
struct mtk_pcie_port *port = platform_get_drvdata(pdev); |
|
struct pci_host_bridge *host = pci_host_bridge_from_priv(port); |
|
|
|
pci_lock_rescan_remove(); |
|
pci_stop_root_bus(host->bus); |
|
pci_remove_root_bus(host->bus); |
|
pci_unlock_rescan_remove(); |
|
|
|
mtk_pcie_irq_teardown(port); |
|
mtk_pcie_power_down(port); |
|
|
|
return 0; |
|
} |
|
|
|
static void __maybe_unused mtk_pcie_irq_save(struct mtk_pcie_port *port) |
|
{ |
|
int i; |
|
|
|
raw_spin_lock(&port->irq_lock); |
|
|
|
port->saved_irq_state = readl_relaxed(port->base + PCIE_INT_ENABLE_REG); |
|
|
|
for (i = 0; i < PCIE_MSI_SET_NUM; i++) { |
|
struct mtk_msi_set *msi_set = &port->msi_sets[i]; |
|
|
|
msi_set->saved_irq_state = readl_relaxed(msi_set->base + |
|
PCIE_MSI_SET_ENABLE_OFFSET); |
|
} |
|
|
|
raw_spin_unlock(&port->irq_lock); |
|
} |
|
|
|
static void __maybe_unused mtk_pcie_irq_restore(struct mtk_pcie_port *port) |
|
{ |
|
int i; |
|
|
|
raw_spin_lock(&port->irq_lock); |
|
|
|
writel_relaxed(port->saved_irq_state, port->base + PCIE_INT_ENABLE_REG); |
|
|
|
for (i = 0; i < PCIE_MSI_SET_NUM; i++) { |
|
struct mtk_msi_set *msi_set = &port->msi_sets[i]; |
|
|
|
writel_relaxed(msi_set->saved_irq_state, |
|
msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); |
|
} |
|
|
|
raw_spin_unlock(&port->irq_lock); |
|
} |
|
|
|
static int __maybe_unused mtk_pcie_turn_off_link(struct mtk_pcie_port *port) |
|
{ |
|
u32 val; |
|
|
|
val = readl_relaxed(port->base + PCIE_ICMD_PM_REG); |
|
val |= PCIE_TURN_OFF_LINK; |
|
writel_relaxed(val, port->base + PCIE_ICMD_PM_REG); |
|
|
|
/* Check the link is L2 */ |
|
return readl_poll_timeout(port->base + PCIE_LTSSM_STATUS_REG, val, |
|
(PCIE_LTSSM_STATE(val) == |
|
PCIE_LTSSM_STATE_L2_IDLE), 20, |
|
50 * USEC_PER_MSEC); |
|
} |
|
|
|
static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev) |
|
{ |
|
struct mtk_pcie_port *port = dev_get_drvdata(dev); |
|
int err; |
|
u32 val; |
|
|
|
/* Trigger link to L2 state */ |
|
err = mtk_pcie_turn_off_link(port); |
|
if (err) { |
|
dev_err(port->dev, "cannot enter L2 state\n"); |
|
return err; |
|
} |
|
|
|
/* Pull down the PERST# pin */ |
|
val = readl_relaxed(port->base + PCIE_RST_CTRL_REG); |
|
val |= PCIE_PE_RSTB; |
|
writel_relaxed(val, port->base + PCIE_RST_CTRL_REG); |
|
|
|
dev_dbg(port->dev, "entered L2 states successfully"); |
|
|
|
mtk_pcie_irq_save(port); |
|
mtk_pcie_power_down(port); |
|
|
|
return 0; |
|
} |
|
|
|
static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev) |
|
{ |
|
struct mtk_pcie_port *port = dev_get_drvdata(dev); |
|
int err; |
|
|
|
err = mtk_pcie_power_up(port); |
|
if (err) |
|
return err; |
|
|
|
err = mtk_pcie_startup_port(port); |
|
if (err) { |
|
mtk_pcie_power_down(port); |
|
return err; |
|
} |
|
|
|
mtk_pcie_irq_restore(port); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct dev_pm_ops mtk_pcie_pm_ops = { |
|
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq, |
|
mtk_pcie_resume_noirq) |
|
}; |
|
|
|
static const struct of_device_id mtk_pcie_of_match[] = { |
|
{ .compatible = "mediatek,mt8192-pcie" }, |
|
{}, |
|
}; |
|
|
|
static struct platform_driver mtk_pcie_driver = { |
|
.probe = mtk_pcie_probe, |
|
.remove = mtk_pcie_remove, |
|
.driver = { |
|
.name = "mtk-pcie", |
|
.of_match_table = mtk_pcie_of_match, |
|
.pm = &mtk_pcie_pm_ops, |
|
}, |
|
}; |
|
|
|
module_platform_driver(mtk_pcie_driver); |
|
MODULE_LICENSE("GPL v2");
|
|
|