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85 lines
1.8 KiB
85 lines
1.8 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Driver for the Conexant CX25821 PCIe bridge |
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* |
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* Copyright (C) 2009 Conexant Systems Inc. |
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* Authors <[email protected]>, <[email protected]> |
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*/ |
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#include <linux/module.h> |
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#include "cx25821.h" |
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/********************* GPIO stuffs *********************/ |
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void cx25821_set_gpiopin_direction(struct cx25821_dev *dev, |
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int pin_number, int pin_logic_value) |
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{ |
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int bit = pin_number; |
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u32 gpio_oe_reg = GPIO_LO_OE; |
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u32 gpio_register = 0; |
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u32 value = 0; |
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/* Check for valid pinNumber */ |
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if (pin_number >= 47) |
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return; |
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if (pin_number > 31) { |
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bit = pin_number - 31; |
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gpio_oe_reg = GPIO_HI_OE; |
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} |
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/* Here we will make sure that the GPIOs 0 and 1 are output. keep the |
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* rest as is */ |
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gpio_register = cx_read(gpio_oe_reg); |
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if (pin_logic_value == 1) |
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value = gpio_register | Set_GPIO_Bit(bit); |
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else |
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value = gpio_register & Clear_GPIO_Bit(bit); |
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cx_write(gpio_oe_reg, value); |
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} |
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EXPORT_SYMBOL(cx25821_set_gpiopin_direction); |
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static void cx25821_set_gpiopin_logicvalue(struct cx25821_dev *dev, |
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int pin_number, int pin_logic_value) |
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{ |
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int bit = pin_number; |
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u32 gpio_reg = GPIO_LO; |
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u32 value = 0; |
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/* Check for valid pinNumber */ |
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if (pin_number >= 47) |
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return; |
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/* change to output direction */ |
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cx25821_set_gpiopin_direction(dev, pin_number, 0); |
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if (pin_number > 31) { |
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bit = pin_number - 31; |
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gpio_reg = GPIO_HI; |
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} |
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value = cx_read(gpio_reg); |
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if (pin_logic_value == 0) |
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value &= Clear_GPIO_Bit(bit); |
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else |
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value |= Set_GPIO_Bit(bit); |
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cx_write(gpio_reg, value); |
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} |
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void cx25821_gpio_init(struct cx25821_dev *dev) |
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{ |
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if (dev == NULL) |
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return; |
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switch (dev->board) { |
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case CX25821_BOARD_CONEXANT_ATHENA10: |
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default: |
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/* set GPIO 5 to select the path for Medusa/Athena */ |
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cx25821_set_gpiopin_logicvalue(dev, 5, 1); |
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msleep(20); |
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break; |
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} |
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}
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