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160 lines
5.3 KiB
160 lines
5.3 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Aptina Sensor PLL Configuration |
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* |
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* Copyright (C) 2012 Laurent Pinchart <[email protected]> |
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*/ |
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#include <linux/device.h> |
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#include <linux/gcd.h> |
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#include <linux/kernel.h> |
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#include <linux/lcm.h> |
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#include <linux/module.h> |
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#include "aptina-pll.h" |
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int aptina_pll_calculate(struct device *dev, |
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const struct aptina_pll_limits *limits, |
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struct aptina_pll *pll) |
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{ |
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unsigned int mf_min; |
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unsigned int mf_max; |
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unsigned int p1_min; |
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unsigned int p1_max; |
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unsigned int p1; |
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unsigned int div; |
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dev_dbg(dev, "PLL: ext clock %u pix clock %u\n", |
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pll->ext_clock, pll->pix_clock); |
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if (pll->ext_clock < limits->ext_clock_min || |
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pll->ext_clock > limits->ext_clock_max) { |
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dev_err(dev, "pll: invalid external clock frequency.\n"); |
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return -EINVAL; |
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} |
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if (pll->pix_clock == 0 || pll->pix_clock > limits->pix_clock_max) { |
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dev_err(dev, "pll: invalid pixel clock frequency.\n"); |
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return -EINVAL; |
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} |
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/* Compute the multiplier M and combined N*P1 divisor. */ |
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div = gcd(pll->pix_clock, pll->ext_clock); |
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pll->m = pll->pix_clock / div; |
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div = pll->ext_clock / div; |
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/* We now have the smallest M and N*P1 values that will result in the |
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* desired pixel clock frequency, but they might be out of the valid |
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* range. Compute the factor by which we should multiply them given the |
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* following constraints: |
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* |
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* - minimum/maximum multiplier |
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* - minimum/maximum multiplier output clock frequency assuming the |
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* minimum/maximum N value |
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* - minimum/maximum combined N*P1 divisor |
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*/ |
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mf_min = DIV_ROUND_UP(limits->m_min, pll->m); |
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mf_min = max(mf_min, limits->out_clock_min / |
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(pll->ext_clock / limits->n_min * pll->m)); |
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mf_min = max(mf_min, limits->n_min * limits->p1_min / div); |
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mf_max = limits->m_max / pll->m; |
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mf_max = min(mf_max, limits->out_clock_max / |
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(pll->ext_clock / limits->n_max * pll->m)); |
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mf_max = min(mf_max, DIV_ROUND_UP(limits->n_max * limits->p1_max, div)); |
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dev_dbg(dev, "pll: mf min %u max %u\n", mf_min, mf_max); |
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if (mf_min > mf_max) { |
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dev_err(dev, "pll: no valid combined N*P1 divisor.\n"); |
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return -EINVAL; |
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} |
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/* |
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* We're looking for the highest acceptable P1 value for which a |
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* multiplier factor MF exists that fulfills the following conditions: |
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* |
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* 1. p1 is in the [p1_min, p1_max] range given by the limits and is |
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* even |
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* 2. mf is in the [mf_min, mf_max] range computed above |
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* 3. div * mf is a multiple of p1, in order to compute |
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* n = div * mf / p1 |
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* m = pll->m * mf |
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* 4. the internal clock frequency, given by ext_clock / n, is in the |
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* [int_clock_min, int_clock_max] range given by the limits |
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* 5. the output clock frequency, given by ext_clock / n * m, is in the |
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* [out_clock_min, out_clock_max] range given by the limits |
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* |
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* The first naive approach is to iterate over all p1 values acceptable |
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* according to (1) and all mf values acceptable according to (2), and |
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* stop at the first combination that fulfills (3), (4) and (5). This |
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* has a O(n^2) complexity. |
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* |
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* Instead of iterating over all mf values in the [mf_min, mf_max] range |
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* we can compute the mf increment between two acceptable values |
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* according to (3) with |
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* |
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* mf_inc = p1 / gcd(div, p1) (6) |
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* |
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* and round the minimum up to the nearest multiple of mf_inc. This will |
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* restrict the number of mf values to be checked. |
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* |
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* Furthermore, conditions (4) and (5) only restrict the range of |
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* acceptable p1 and mf values by modifying the minimum and maximum |
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* limits. (5) can be expressed as |
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* |
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* ext_clock / (div * mf / p1) * m * mf >= out_clock_min |
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* ext_clock / (div * mf / p1) * m * mf <= out_clock_max |
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* |
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* or |
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* |
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* p1 >= out_clock_min * div / (ext_clock * m) (7) |
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* p1 <= out_clock_max * div / (ext_clock * m) |
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* |
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* Similarly, (4) can be expressed as |
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* |
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* mf >= ext_clock * p1 / (int_clock_max * div) (8) |
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* mf <= ext_clock * p1 / (int_clock_min * div) |
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* |
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* We can thus iterate over the restricted p1 range defined by the |
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* combination of (1) and (7), and then compute the restricted mf range |
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* defined by the combination of (2), (6) and (8). If the resulting mf |
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* range is not empty, any value in the mf range is acceptable. We thus |
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* select the mf lwoer bound and the corresponding p1 value. |
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*/ |
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if (limits->p1_min == 0) { |
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dev_err(dev, "pll: P1 minimum value must be >0.\n"); |
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return -EINVAL; |
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} |
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p1_min = max(limits->p1_min, DIV_ROUND_UP(limits->out_clock_min * div, |
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pll->ext_clock * pll->m)); |
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p1_max = min(limits->p1_max, limits->out_clock_max * div / |
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(pll->ext_clock * pll->m)); |
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for (p1 = p1_max & ~1; p1 >= p1_min; p1 -= 2) { |
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unsigned int mf_inc = p1 / gcd(div, p1); |
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unsigned int mf_high; |
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unsigned int mf_low; |
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mf_low = roundup(max(mf_min, DIV_ROUND_UP(pll->ext_clock * p1, |
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limits->int_clock_max * div)), mf_inc); |
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mf_high = min(mf_max, pll->ext_clock * p1 / |
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(limits->int_clock_min * div)); |
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if (mf_low > mf_high) |
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continue; |
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pll->n = div * mf_low / p1; |
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pll->m *= mf_low; |
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pll->p1 = p1; |
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dev_dbg(dev, "PLL: N %u M %u P1 %u\n", pll->n, pll->m, pll->p1); |
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return 0; |
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} |
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dev_err(dev, "pll: no valid N and P1 divisors found.\n"); |
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return -EINVAL; |
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} |
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EXPORT_SYMBOL_GPL(aptina_pll_calculate); |
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MODULE_DESCRIPTION("Aptina PLL Helpers"); |
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MODULE_AUTHOR("Laurent Pinchart <[email protected]>"); |
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MODULE_LICENSE("GPL v2");
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