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206 lines
6.0 KiB
206 lines
6.0 KiB
/* |
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* Allwinner A1X SoCs IRQ chip driver. |
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* |
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* Copyright (C) 2012 Maxime Ripard |
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* |
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* Maxime Ripard <[email protected]> |
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* |
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* Based on code from |
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com> |
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* Benn Huang <[email protected]> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/irqchip.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <asm/exception.h> |
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#define SUN4I_IRQ_VECTOR_REG 0x00 |
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#define SUN4I_IRQ_PROTECTION_REG 0x08 |
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#define SUN4I_IRQ_NMI_CTRL_REG 0x0c |
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#define SUN4I_IRQ_PENDING_REG(x) (0x10 + 0x4 * x) |
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#define SUN4I_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x) |
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#define SUN4I_IRQ_ENABLE_REG(data, x) ((data)->enable_reg_offset + 0x4 * x) |
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#define SUN4I_IRQ_MASK_REG(data, x) ((data)->mask_reg_offset + 0x4 * x) |
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#define SUN4I_IRQ_ENABLE_REG_OFFSET 0x40 |
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#define SUN4I_IRQ_MASK_REG_OFFSET 0x50 |
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#define SUNIV_IRQ_ENABLE_REG_OFFSET 0x20 |
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#define SUNIV_IRQ_MASK_REG_OFFSET 0x30 |
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struct sun4i_irq_chip_data { |
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void __iomem *irq_base; |
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struct irq_domain *irq_domain; |
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u32 enable_reg_offset; |
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u32 mask_reg_offset; |
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}; |
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static struct sun4i_irq_chip_data *irq_ic_data; |
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static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs); |
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static void sun4i_irq_ack(struct irq_data *irqd) |
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{ |
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unsigned int irq = irqd_to_hwirq(irqd); |
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if (irq != 0) |
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return; /* Only IRQ 0 / the ENMI needs to be acked */ |
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writel(BIT(0), irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0)); |
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} |
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static void sun4i_irq_mask(struct irq_data *irqd) |
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{ |
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unsigned int irq = irqd_to_hwirq(irqd); |
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unsigned int irq_off = irq % 32; |
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int reg = irq / 32; |
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u32 val; |
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val = readl(irq_ic_data->irq_base + |
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SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); |
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writel(val & ~(1 << irq_off), |
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irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); |
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} |
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static void sun4i_irq_unmask(struct irq_data *irqd) |
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{ |
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unsigned int irq = irqd_to_hwirq(irqd); |
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unsigned int irq_off = irq % 32; |
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int reg = irq / 32; |
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u32 val; |
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val = readl(irq_ic_data->irq_base + |
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SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); |
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writel(val | (1 << irq_off), |
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irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); |
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} |
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static struct irq_chip sun4i_irq_chip = { |
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.name = "sun4i_irq", |
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.irq_eoi = sun4i_irq_ack, |
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.irq_mask = sun4i_irq_mask, |
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.irq_unmask = sun4i_irq_unmask, |
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.flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED, |
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}; |
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static int sun4i_irq_map(struct irq_domain *d, unsigned int virq, |
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irq_hw_number_t hw) |
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{ |
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irq_set_chip_and_handler(virq, &sun4i_irq_chip, handle_fasteoi_irq); |
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irq_set_probe(virq); |
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return 0; |
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} |
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static const struct irq_domain_ops sun4i_irq_ops = { |
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.map = sun4i_irq_map, |
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.xlate = irq_domain_xlate_onecell, |
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}; |
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static int __init sun4i_of_init(struct device_node *node, |
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struct device_node *parent) |
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{ |
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irq_ic_data->irq_base = of_iomap(node, 0); |
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if (!irq_ic_data->irq_base) |
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panic("%pOF: unable to map IC registers\n", |
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node); |
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/* Disable all interrupts */ |
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writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 0)); |
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writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 1)); |
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writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 2)); |
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/* Unmask all the interrupts, ENABLE_REG(x) is used for masking */ |
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writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 0)); |
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writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 1)); |
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writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 2)); |
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/* Clear all the pending interrupts */ |
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writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0)); |
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writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(1)); |
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writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(2)); |
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/* Enable protection mode */ |
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writel(0x01, irq_ic_data->irq_base + SUN4I_IRQ_PROTECTION_REG); |
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/* Configure the external interrupt source type */ |
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writel(0x00, irq_ic_data->irq_base + SUN4I_IRQ_NMI_CTRL_REG); |
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irq_ic_data->irq_domain = irq_domain_add_linear(node, 3 * 32, |
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&sun4i_irq_ops, NULL); |
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if (!irq_ic_data->irq_domain) |
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panic("%pOF: unable to create IRQ domain\n", node); |
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set_handle_irq(sun4i_handle_irq); |
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return 0; |
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} |
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static int __init sun4i_ic_of_init(struct device_node *node, |
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struct device_node *parent) |
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{ |
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irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL); |
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if (!irq_ic_data) { |
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pr_err("kzalloc failed!\n"); |
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return -ENOMEM; |
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} |
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irq_ic_data->enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET; |
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irq_ic_data->mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET; |
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return sun4i_of_init(node, parent); |
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} |
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IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_ic_of_init); |
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static int __init suniv_ic_of_init(struct device_node *node, |
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struct device_node *parent) |
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{ |
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irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL); |
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if (!irq_ic_data) { |
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pr_err("kzalloc failed!\n"); |
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return -ENOMEM; |
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} |
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irq_ic_data->enable_reg_offset = SUNIV_IRQ_ENABLE_REG_OFFSET; |
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irq_ic_data->mask_reg_offset = SUNIV_IRQ_MASK_REG_OFFSET; |
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return sun4i_of_init(node, parent); |
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} |
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IRQCHIP_DECLARE(allwinner_sunvi_ic, "allwinner,suniv-f1c100s-ic", |
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suniv_ic_of_init); |
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static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs) |
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{ |
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u32 hwirq; |
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/* |
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* hwirq == 0 can mean one of 3 things: |
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* 1) no more irqs pending |
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* 2) irq 0 pending |
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* 3) spurious irq |
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* So if we immediately get a reading of 0, check the irq-pending reg |
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* to differentiate between 2 and 3. We only do this once to avoid |
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* the extra check in the common case of 1 happening after having |
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* read the vector-reg once. |
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*/ |
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hwirq = readl(irq_ic_data->irq_base + SUN4I_IRQ_VECTOR_REG) >> 2; |
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if (hwirq == 0 && |
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!(readl(irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0)) & |
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BIT(0))) |
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return; |
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do { |
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handle_domain_irq(irq_ic_data->irq_domain, hwirq, regs); |
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hwirq = readl(irq_ic_data->irq_base + |
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SUN4I_IRQ_VECTOR_REG) >> 2; |
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} while (hwirq != 0); |
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}
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