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67 lines
1.9 KiB
67 lines
1.9 KiB
/* SPDX-License-Identifier: BSD-3-Clause */ |
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/* |
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* Copyright (c) 2020, MIPI Alliance, Inc. |
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* |
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* Author: Nicolas Pitre <[email protected]> |
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* |
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* Common command/response related stuff |
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*/ |
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#ifndef CMD_H |
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#define CMD_H |
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/* |
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* Those bits are common to all descriptor formats and |
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* may be manipulated by the core code. |
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*/ |
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#define CMD_0_TOC W0_BIT_(31) |
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#define CMD_0_ROC W0_BIT_(30) |
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#define CMD_0_ATTR W0_MASK(2, 0) |
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/* |
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* Response Descriptor Structure |
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*/ |
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#define RESP_STATUS(resp) FIELD_GET(GENMASK(31, 28), resp) |
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#define RESP_TID(resp) FIELD_GET(GENMASK(27, 24), resp) |
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#define RESP_DATA_LENGTH(resp) FIELD_GET(GENMASK(21, 0), resp) |
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#define RESP_ERR_FIELD GENMASK(31, 28) |
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enum hci_resp_err { |
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RESP_SUCCESS = 0x0, |
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RESP_ERR_CRC = 0x1, |
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RESP_ERR_PARITY = 0x2, |
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RESP_ERR_FRAME = 0x3, |
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RESP_ERR_ADDR_HEADER = 0x4, |
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RESP_ERR_BCAST_NACK_7E = 0x4, |
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RESP_ERR_NACK = 0x5, |
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RESP_ERR_OVL = 0x6, |
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RESP_ERR_I3C_SHORT_READ = 0x7, |
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RESP_ERR_HC_TERMINATED = 0x8, |
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RESP_ERR_I2C_WR_DATA_NACK = 0x9, |
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RESP_ERR_BUS_XFER_ABORTED = 0x9, |
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RESP_ERR_NOT_SUPPORTED = 0xa, |
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RESP_ERR_ABORTED_WITH_CRC = 0xb, |
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/* 0xc to 0xf are reserved for transfer specific errors */ |
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}; |
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/* TID generation (4 bits wide in all cases) */ |
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#define hci_get_tid(bits) \ |
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(atomic_inc_return_relaxed(&hci->next_cmd_tid) % (1U << 4)) |
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/* This abstracts operations with our command descriptor formats */ |
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struct hci_cmd_ops { |
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int (*prep_ccc)(struct i3c_hci *hci, struct hci_xfer *xfer, |
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u8 ccc_addr, u8 ccc_cmd, bool raw); |
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void (*prep_i3c_xfer)(struct i3c_hci *hci, struct i3c_dev_desc *dev, |
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struct hci_xfer *xfer); |
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void (*prep_i2c_xfer)(struct i3c_hci *hci, struct i2c_dev_desc *dev, |
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struct hci_xfer *xfer); |
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int (*perform_daa)(struct i3c_hci *hci); |
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}; |
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/* Our various instances */ |
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extern const struct hci_cmd_ops mipi_i3c_hci_cmd_v1; |
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extern const struct hci_cmd_ops mipi_i3c_hci_cmd_v2; |
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#endif
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