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595 lines
15 KiB
595 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* jc42.c - driver for Jedec JC42.4 compliant temperature sensors |
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* |
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* Copyright (c) 2010 Ericsson AB. |
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* |
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* Derived from lm77.c by Andras BALI <[email protected]>. |
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* |
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* JC42.4 compliant temperature sensors are typically used on memory modules. |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/module.h> |
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#include <linux/init.h> |
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#include <linux/slab.h> |
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#include <linux/jiffies.h> |
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#include <linux/i2c.h> |
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#include <linux/hwmon.h> |
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#include <linux/err.h> |
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#include <linux/mutex.h> |
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#include <linux/of.h> |
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/* Addresses to scan */ |
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static const unsigned short normal_i2c[] = { |
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0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END }; |
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/* JC42 registers. All registers are 16 bit. */ |
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#define JC42_REG_CAP 0x00 |
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#define JC42_REG_CONFIG 0x01 |
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#define JC42_REG_TEMP_UPPER 0x02 |
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#define JC42_REG_TEMP_LOWER 0x03 |
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#define JC42_REG_TEMP_CRITICAL 0x04 |
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#define JC42_REG_TEMP 0x05 |
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#define JC42_REG_MANID 0x06 |
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#define JC42_REG_DEVICEID 0x07 |
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#define JC42_REG_SMBUS 0x22 /* NXP and Atmel, possibly others? */ |
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/* Status bits in temperature register */ |
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#define JC42_ALARM_CRIT_BIT 15 |
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#define JC42_ALARM_MAX_BIT 14 |
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#define JC42_ALARM_MIN_BIT 13 |
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/* Configuration register defines */ |
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#define JC42_CFG_CRIT_ONLY (1 << 2) |
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#define JC42_CFG_TCRIT_LOCK (1 << 6) |
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#define JC42_CFG_EVENT_LOCK (1 << 7) |
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#define JC42_CFG_SHUTDOWN (1 << 8) |
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#define JC42_CFG_HYST_SHIFT 9 |
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#define JC42_CFG_HYST_MASK (0x03 << 9) |
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/* Capabilities */ |
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#define JC42_CAP_RANGE (1 << 2) |
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/* Manufacturer IDs */ |
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#define ADT_MANID 0x11d4 /* Analog Devices */ |
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#define ATMEL_MANID 0x001f /* Atmel */ |
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#define ATMEL_MANID2 0x1114 /* Atmel */ |
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#define MAX_MANID 0x004d /* Maxim */ |
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#define IDT_MANID 0x00b3 /* IDT */ |
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#define MCP_MANID 0x0054 /* Microchip */ |
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#define NXP_MANID 0x1131 /* NXP Semiconductors */ |
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#define ONS_MANID 0x1b09 /* ON Semiconductor */ |
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#define STM_MANID 0x104a /* ST Microelectronics */ |
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#define GT_MANID 0x1c68 /* Giantec */ |
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#define GT_MANID2 0x132d /* Giantec, 2nd mfg ID */ |
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/* SMBUS register */ |
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#define SMBUS_STMOUT BIT(7) /* SMBus time-out, active low */ |
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/* Supported chips */ |
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/* Analog Devices */ |
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#define ADT7408_DEVID 0x0801 |
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#define ADT7408_DEVID_MASK 0xffff |
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/* Atmel */ |
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#define AT30TS00_DEVID 0x8201 |
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#define AT30TS00_DEVID_MASK 0xffff |
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#define AT30TSE004_DEVID 0x2200 |
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#define AT30TSE004_DEVID_MASK 0xffff |
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/* Giantec */ |
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#define GT30TS00_DEVID 0x2200 |
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#define GT30TS00_DEVID_MASK 0xff00 |
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#define GT34TS02_DEVID 0x3300 |
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#define GT34TS02_DEVID_MASK 0xff00 |
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/* IDT */ |
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#define TSE2004_DEVID 0x2200 |
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#define TSE2004_DEVID_MASK 0xff00 |
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#define TS3000_DEVID 0x2900 /* Also matches TSE2002 */ |
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#define TS3000_DEVID_MASK 0xff00 |
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#define TS3001_DEVID 0x3000 |
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#define TS3001_DEVID_MASK 0xff00 |
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/* Maxim */ |
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#define MAX6604_DEVID 0x3e00 |
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#define MAX6604_DEVID_MASK 0xffff |
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/* Microchip */ |
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#define MCP9804_DEVID 0x0200 |
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#define MCP9804_DEVID_MASK 0xfffc |
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#define MCP9808_DEVID 0x0400 |
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#define MCP9808_DEVID_MASK 0xfffc |
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#define MCP98242_DEVID 0x2000 |
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#define MCP98242_DEVID_MASK 0xfffc |
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#define MCP98243_DEVID 0x2100 |
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#define MCP98243_DEVID_MASK 0xfffc |
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#define MCP98244_DEVID 0x2200 |
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#define MCP98244_DEVID_MASK 0xfffc |
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#define MCP9843_DEVID 0x0000 /* Also matches mcp9805 */ |
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#define MCP9843_DEVID_MASK 0xfffe |
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/* NXP */ |
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#define SE97_DEVID 0xa200 |
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#define SE97_DEVID_MASK 0xfffc |
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#define SE98_DEVID 0xa100 |
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#define SE98_DEVID_MASK 0xfffc |
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/* ON Semiconductor */ |
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#define CAT6095_DEVID 0x0800 /* Also matches CAT34TS02 */ |
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#define CAT6095_DEVID_MASK 0xffe0 |
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#define CAT34TS02C_DEVID 0x0a00 |
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#define CAT34TS02C_DEVID_MASK 0xfff0 |
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#define CAT34TS04_DEVID 0x2200 |
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#define CAT34TS04_DEVID_MASK 0xfff0 |
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/* ST Microelectronics */ |
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#define STTS424_DEVID 0x0101 |
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#define STTS424_DEVID_MASK 0xffff |
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#define STTS424E_DEVID 0x0000 |
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#define STTS424E_DEVID_MASK 0xfffe |
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#define STTS2002_DEVID 0x0300 |
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#define STTS2002_DEVID_MASK 0xffff |
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#define STTS2004_DEVID 0x2201 |
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#define STTS2004_DEVID_MASK 0xffff |
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#define STTS3000_DEVID 0x0200 |
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#define STTS3000_DEVID_MASK 0xffff |
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static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 }; |
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struct jc42_chips { |
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u16 manid; |
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u16 devid; |
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u16 devid_mask; |
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}; |
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static struct jc42_chips jc42_chips[] = { |
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{ ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK }, |
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{ ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK }, |
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{ ATMEL_MANID2, AT30TSE004_DEVID, AT30TSE004_DEVID_MASK }, |
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{ GT_MANID, GT30TS00_DEVID, GT30TS00_DEVID_MASK }, |
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{ GT_MANID2, GT34TS02_DEVID, GT34TS02_DEVID_MASK }, |
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{ IDT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK }, |
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{ IDT_MANID, TS3000_DEVID, TS3000_DEVID_MASK }, |
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{ IDT_MANID, TS3001_DEVID, TS3001_DEVID_MASK }, |
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{ MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK }, |
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{ MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK }, |
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{ MCP_MANID, MCP9808_DEVID, MCP9808_DEVID_MASK }, |
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{ MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK }, |
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{ MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK }, |
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{ MCP_MANID, MCP98244_DEVID, MCP98244_DEVID_MASK }, |
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{ MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK }, |
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{ NXP_MANID, SE97_DEVID, SE97_DEVID_MASK }, |
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{ ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK }, |
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{ ONS_MANID, CAT34TS02C_DEVID, CAT34TS02C_DEVID_MASK }, |
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{ ONS_MANID, CAT34TS04_DEVID, CAT34TS04_DEVID_MASK }, |
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{ NXP_MANID, SE98_DEVID, SE98_DEVID_MASK }, |
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{ STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK }, |
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{ STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK }, |
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{ STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK }, |
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{ STM_MANID, STTS2004_DEVID, STTS2004_DEVID_MASK }, |
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{ STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK }, |
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}; |
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enum temp_index { |
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t_input = 0, |
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t_crit, |
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t_min, |
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t_max, |
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t_num_temp |
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}; |
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static const u8 temp_regs[t_num_temp] = { |
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[t_input] = JC42_REG_TEMP, |
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[t_crit] = JC42_REG_TEMP_CRITICAL, |
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[t_min] = JC42_REG_TEMP_LOWER, |
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[t_max] = JC42_REG_TEMP_UPPER, |
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}; |
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/* Each client has this additional data */ |
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struct jc42_data { |
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struct i2c_client *client; |
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struct mutex update_lock; /* protect register access */ |
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bool extended; /* true if extended range supported */ |
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bool valid; |
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unsigned long last_updated; /* In jiffies */ |
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u16 orig_config; /* original configuration */ |
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u16 config; /* current configuration */ |
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u16 temp[t_num_temp];/* Temperatures */ |
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}; |
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#define JC42_TEMP_MIN_EXTENDED (-40000) |
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#define JC42_TEMP_MIN 0 |
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#define JC42_TEMP_MAX 125000 |
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static u16 jc42_temp_to_reg(long temp, bool extended) |
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{ |
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int ntemp = clamp_val(temp, |
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extended ? JC42_TEMP_MIN_EXTENDED : |
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JC42_TEMP_MIN, JC42_TEMP_MAX); |
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/* convert from 0.001 to 0.0625 resolution */ |
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return (ntemp * 2 / 125) & 0x1fff; |
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} |
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static int jc42_temp_from_reg(s16 reg) |
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{ |
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reg = sign_extend32(reg, 12); |
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/* convert from 0.0625 to 0.001 resolution */ |
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return reg * 125 / 2; |
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} |
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static struct jc42_data *jc42_update_device(struct device *dev) |
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{ |
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struct jc42_data *data = dev_get_drvdata(dev); |
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struct i2c_client *client = data->client; |
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struct jc42_data *ret = data; |
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int i, val; |
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mutex_lock(&data->update_lock); |
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if (time_after(jiffies, data->last_updated + HZ) || !data->valid) { |
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for (i = 0; i < t_num_temp; i++) { |
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val = i2c_smbus_read_word_swapped(client, temp_regs[i]); |
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if (val < 0) { |
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ret = ERR_PTR(val); |
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goto abort; |
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} |
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data->temp[i] = val; |
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} |
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data->last_updated = jiffies; |
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data->valid = true; |
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} |
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abort: |
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mutex_unlock(&data->update_lock); |
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return ret; |
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} |
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static int jc42_read(struct device *dev, enum hwmon_sensor_types type, |
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u32 attr, int channel, long *val) |
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{ |
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struct jc42_data *data = jc42_update_device(dev); |
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int temp, hyst; |
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if (IS_ERR(data)) |
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return PTR_ERR(data); |
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switch (attr) { |
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case hwmon_temp_input: |
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*val = jc42_temp_from_reg(data->temp[t_input]); |
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return 0; |
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case hwmon_temp_min: |
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*val = jc42_temp_from_reg(data->temp[t_min]); |
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return 0; |
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case hwmon_temp_max: |
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*val = jc42_temp_from_reg(data->temp[t_max]); |
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return 0; |
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case hwmon_temp_crit: |
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*val = jc42_temp_from_reg(data->temp[t_crit]); |
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return 0; |
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case hwmon_temp_max_hyst: |
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temp = jc42_temp_from_reg(data->temp[t_max]); |
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hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK) |
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>> JC42_CFG_HYST_SHIFT]; |
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*val = temp - hyst; |
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return 0; |
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case hwmon_temp_crit_hyst: |
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temp = jc42_temp_from_reg(data->temp[t_crit]); |
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hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK) |
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>> JC42_CFG_HYST_SHIFT]; |
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*val = temp - hyst; |
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return 0; |
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case hwmon_temp_min_alarm: |
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*val = (data->temp[t_input] >> JC42_ALARM_MIN_BIT) & 1; |
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return 0; |
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case hwmon_temp_max_alarm: |
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*val = (data->temp[t_input] >> JC42_ALARM_MAX_BIT) & 1; |
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return 0; |
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case hwmon_temp_crit_alarm: |
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*val = (data->temp[t_input] >> JC42_ALARM_CRIT_BIT) & 1; |
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return 0; |
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default: |
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return -EOPNOTSUPP; |
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} |
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} |
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static int jc42_write(struct device *dev, enum hwmon_sensor_types type, |
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u32 attr, int channel, long val) |
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{ |
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struct jc42_data *data = dev_get_drvdata(dev); |
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struct i2c_client *client = data->client; |
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int diff, hyst; |
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int ret; |
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mutex_lock(&data->update_lock); |
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switch (attr) { |
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case hwmon_temp_min: |
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data->temp[t_min] = jc42_temp_to_reg(val, data->extended); |
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ret = i2c_smbus_write_word_swapped(client, temp_regs[t_min], |
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data->temp[t_min]); |
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break; |
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case hwmon_temp_max: |
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data->temp[t_max] = jc42_temp_to_reg(val, data->extended); |
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ret = i2c_smbus_write_word_swapped(client, temp_regs[t_max], |
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data->temp[t_max]); |
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break; |
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case hwmon_temp_crit: |
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data->temp[t_crit] = jc42_temp_to_reg(val, data->extended); |
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ret = i2c_smbus_write_word_swapped(client, temp_regs[t_crit], |
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data->temp[t_crit]); |
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break; |
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case hwmon_temp_crit_hyst: |
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/* |
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* JC42.4 compliant chips only support four hysteresis values. |
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* Pick best choice and go from there. |
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*/ |
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val = clamp_val(val, (data->extended ? JC42_TEMP_MIN_EXTENDED |
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: JC42_TEMP_MIN) - 6000, |
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JC42_TEMP_MAX); |
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diff = jc42_temp_from_reg(data->temp[t_crit]) - val; |
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hyst = 0; |
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if (diff > 0) { |
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if (diff < 2250) |
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hyst = 1; /* 1.5 degrees C */ |
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else if (diff < 4500) |
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hyst = 2; /* 3.0 degrees C */ |
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else |
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hyst = 3; /* 6.0 degrees C */ |
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} |
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data->config = (data->config & ~JC42_CFG_HYST_MASK) | |
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(hyst << JC42_CFG_HYST_SHIFT); |
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ret = i2c_smbus_write_word_swapped(data->client, |
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JC42_REG_CONFIG, |
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data->config); |
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break; |
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default: |
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ret = -EOPNOTSUPP; |
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break; |
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} |
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mutex_unlock(&data->update_lock); |
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return ret; |
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} |
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static umode_t jc42_is_visible(const void *_data, enum hwmon_sensor_types type, |
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u32 attr, int channel) |
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{ |
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const struct jc42_data *data = _data; |
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unsigned int config = data->config; |
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umode_t mode = 0444; |
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switch (attr) { |
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case hwmon_temp_min: |
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case hwmon_temp_max: |
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if (!(config & JC42_CFG_EVENT_LOCK)) |
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mode |= 0200; |
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break; |
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case hwmon_temp_crit: |
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if (!(config & JC42_CFG_TCRIT_LOCK)) |
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mode |= 0200; |
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break; |
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case hwmon_temp_crit_hyst: |
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if (!(config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK))) |
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mode |= 0200; |
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break; |
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case hwmon_temp_input: |
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case hwmon_temp_max_hyst: |
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case hwmon_temp_min_alarm: |
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case hwmon_temp_max_alarm: |
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case hwmon_temp_crit_alarm: |
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break; |
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default: |
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mode = 0; |
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break; |
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} |
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return mode; |
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} |
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/* Return 0 if detection is successful, -ENODEV otherwise */ |
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static int jc42_detect(struct i2c_client *client, struct i2c_board_info *info) |
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{ |
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struct i2c_adapter *adapter = client->adapter; |
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int i, config, cap, manid, devid; |
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if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | |
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I2C_FUNC_SMBUS_WORD_DATA)) |
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return -ENODEV; |
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cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP); |
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config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG); |
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manid = i2c_smbus_read_word_swapped(client, JC42_REG_MANID); |
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devid = i2c_smbus_read_word_swapped(client, JC42_REG_DEVICEID); |
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if (cap < 0 || config < 0 || manid < 0 || devid < 0) |
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return -ENODEV; |
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if ((cap & 0xff00) || (config & 0xf800)) |
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return -ENODEV; |
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for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) { |
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struct jc42_chips *chip = &jc42_chips[i]; |
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if (manid == chip->manid && |
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(devid & chip->devid_mask) == chip->devid) { |
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strlcpy(info->type, "jc42", I2C_NAME_SIZE); |
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return 0; |
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} |
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} |
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return -ENODEV; |
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} |
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static const struct hwmon_channel_info *jc42_info[] = { |
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HWMON_CHANNEL_INFO(temp, |
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HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX | |
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HWMON_T_CRIT | HWMON_T_MAX_HYST | |
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HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM | |
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HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM), |
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NULL |
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}; |
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static const struct hwmon_ops jc42_hwmon_ops = { |
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.is_visible = jc42_is_visible, |
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.read = jc42_read, |
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.write = jc42_write, |
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}; |
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static const struct hwmon_chip_info jc42_chip_info = { |
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.ops = &jc42_hwmon_ops, |
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.info = jc42_info, |
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}; |
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static int jc42_probe(struct i2c_client *client) |
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{ |
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struct device *dev = &client->dev; |
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struct device *hwmon_dev; |
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struct jc42_data *data; |
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int config, cap; |
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data = devm_kzalloc(dev, sizeof(struct jc42_data), GFP_KERNEL); |
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if (!data) |
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return -ENOMEM; |
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data->client = client; |
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i2c_set_clientdata(client, data); |
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mutex_init(&data->update_lock); |
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cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP); |
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if (cap < 0) |
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return cap; |
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data->extended = !!(cap & JC42_CAP_RANGE); |
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if (device_property_read_bool(dev, "smbus-timeout-disable")) { |
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int smbus; |
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|
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/* |
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* Not all chips support this register, but from a |
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* quick read of various datasheets no chip appears |
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* incompatible with the below attempt to disable |
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* the timeout. And the whole thing is opt-in... |
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*/ |
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smbus = i2c_smbus_read_word_swapped(client, JC42_REG_SMBUS); |
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if (smbus < 0) |
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return smbus; |
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i2c_smbus_write_word_swapped(client, JC42_REG_SMBUS, |
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smbus | SMBUS_STMOUT); |
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} |
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config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG); |
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if (config < 0) |
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return config; |
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|
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data->orig_config = config; |
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if (config & JC42_CFG_SHUTDOWN) { |
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config &= ~JC42_CFG_SHUTDOWN; |
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i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config); |
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} |
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data->config = config; |
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|
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hwmon_dev = devm_hwmon_device_register_with_info(dev, "jc42", |
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data, &jc42_chip_info, |
|
NULL); |
|
return PTR_ERR_OR_ZERO(hwmon_dev); |
|
} |
|
|
|
static int jc42_remove(struct i2c_client *client) |
|
{ |
|
struct jc42_data *data = i2c_get_clientdata(client); |
|
|
|
/* Restore original configuration except hysteresis */ |
|
if ((data->config & ~JC42_CFG_HYST_MASK) != |
|
(data->orig_config & ~JC42_CFG_HYST_MASK)) { |
|
int config; |
|
|
|
config = (data->orig_config & ~JC42_CFG_HYST_MASK) |
|
| (data->config & JC42_CFG_HYST_MASK); |
|
i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config); |
|
} |
|
return 0; |
|
} |
|
|
|
#ifdef CONFIG_PM |
|
|
|
static int jc42_suspend(struct device *dev) |
|
{ |
|
struct jc42_data *data = dev_get_drvdata(dev); |
|
|
|
data->config |= JC42_CFG_SHUTDOWN; |
|
i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG, |
|
data->config); |
|
return 0; |
|
} |
|
|
|
static int jc42_resume(struct device *dev) |
|
{ |
|
struct jc42_data *data = dev_get_drvdata(dev); |
|
|
|
data->config &= ~JC42_CFG_SHUTDOWN; |
|
i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG, |
|
data->config); |
|
return 0; |
|
} |
|
|
|
static const struct dev_pm_ops jc42_dev_pm_ops = { |
|
.suspend = jc42_suspend, |
|
.resume = jc42_resume, |
|
}; |
|
|
|
#define JC42_DEV_PM_OPS (&jc42_dev_pm_ops) |
|
#else |
|
#define JC42_DEV_PM_OPS NULL |
|
#endif /* CONFIG_PM */ |
|
|
|
static const struct i2c_device_id jc42_id[] = { |
|
{ "jc42", 0 }, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(i2c, jc42_id); |
|
|
|
#ifdef CONFIG_OF |
|
static const struct of_device_id jc42_of_ids[] = { |
|
{ .compatible = "jedec,jc-42.4-temp", }, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, jc42_of_ids); |
|
#endif |
|
|
|
static struct i2c_driver jc42_driver = { |
|
.class = I2C_CLASS_SPD | I2C_CLASS_HWMON, |
|
.driver = { |
|
.name = "jc42", |
|
.pm = JC42_DEV_PM_OPS, |
|
.of_match_table = of_match_ptr(jc42_of_ids), |
|
}, |
|
.probe_new = jc42_probe, |
|
.remove = jc42_remove, |
|
.id_table = jc42_id, |
|
.detect = jc42_detect, |
|
.address_list = normal_i2c, |
|
}; |
|
|
|
module_i2c_driver(jc42_driver); |
|
|
|
MODULE_AUTHOR("Guenter Roeck <[email protected]>"); |
|
MODULE_DESCRIPTION("JC42 driver"); |
|
MODULE_LICENSE("GPL");
|
|
|