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25 KiB
1002 lines
25 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* (C) 2001-2004 Dave Jones. |
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* (C) 2002 Padraig Brady. <[email protected]> |
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* |
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* Based upon datasheets & sample CPUs kindly provided by VIA. |
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* |
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* VIA have currently 3 different versions of Longhaul. |
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* Version 1 (Longhaul) uses the BCR2 MSR at 0x1147. |
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* It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0. |
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* Version 2 of longhaul is backward compatible with v1, but adds |
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* LONGHAUL MSR for purpose of both frequency and voltage scaling. |
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* Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C). |
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* Version 3 of longhaul got renamed to Powersaver and redesigned |
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* to use only the POWERSAVER MSR at 0x110a. |
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* It is present in Ezra-T (C5M), Nehemiah (C5X) and above. |
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* It's pretty much the same feature wise to longhaul v2, though |
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* there is provision for scaling FSB too, but this doesn't work |
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* too well in practice so we don't even try to use this. |
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* |
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* BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous* |
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*/ |
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/moduleparam.h> |
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#include <linux/init.h> |
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#include <linux/cpufreq.h> |
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#include <linux/pci.h> |
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#include <linux/slab.h> |
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#include <linux/string.h> |
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#include <linux/delay.h> |
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#include <linux/timex.h> |
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#include <linux/io.h> |
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#include <linux/acpi.h> |
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#include <asm/msr.h> |
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#include <asm/cpu_device_id.h> |
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#include <acpi/processor.h> |
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#include "longhaul.h" |
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#define TYPE_LONGHAUL_V1 1 |
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#define TYPE_LONGHAUL_V2 2 |
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#define TYPE_POWERSAVER 3 |
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#define CPU_SAMUEL 1 |
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#define CPU_SAMUEL2 2 |
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#define CPU_EZRA 3 |
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#define CPU_EZRA_T 4 |
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#define CPU_NEHEMIAH 5 |
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#define CPU_NEHEMIAH_C 6 |
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/* Flags */ |
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#define USE_ACPI_C3 (1 << 1) |
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#define USE_NORTHBRIDGE (1 << 2) |
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static int cpu_model; |
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static unsigned int numscales = 16; |
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static unsigned int fsb; |
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static const struct mV_pos *vrm_mV_table; |
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static const unsigned char *mV_vrm_table; |
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static unsigned int highest_speed, lowest_speed; /* kHz */ |
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static unsigned int minmult, maxmult; |
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static int can_scale_voltage; |
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static struct acpi_processor *pr; |
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static struct acpi_processor_cx *cx; |
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static u32 acpi_regs_addr; |
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static u8 longhaul_flags; |
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static unsigned int longhaul_index; |
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/* Module parameters */ |
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static int scale_voltage; |
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static int disable_acpi_c3; |
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static int revid_errata; |
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static int enable; |
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/* Clock ratios multiplied by 10 */ |
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static int mults[32]; |
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static int eblcr[32]; |
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static int longhaul_version; |
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static struct cpufreq_frequency_table *longhaul_table; |
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static char speedbuffer[8]; |
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static char *print_speed(int speed) |
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{ |
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if (speed < 1000) { |
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snprintf(speedbuffer, sizeof(speedbuffer), "%dMHz", speed); |
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return speedbuffer; |
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} |
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if (speed%1000 == 0) |
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snprintf(speedbuffer, sizeof(speedbuffer), |
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"%dGHz", speed/1000); |
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else |
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snprintf(speedbuffer, sizeof(speedbuffer), |
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"%d.%dGHz", speed/1000, (speed%1000)/100); |
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return speedbuffer; |
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} |
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static unsigned int calc_speed(int mult) |
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{ |
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int khz; |
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khz = (mult/10)*fsb; |
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if (mult%10) |
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khz += fsb/2; |
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khz *= 1000; |
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return khz; |
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} |
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static int longhaul_get_cpu_mult(void) |
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{ |
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unsigned long invalue = 0, lo, hi; |
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rdmsr(MSR_IA32_EBL_CR_POWERON, lo, hi); |
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invalue = (lo & (1<<22|1<<23|1<<24|1<<25))>>22; |
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if (longhaul_version == TYPE_LONGHAUL_V2 || |
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longhaul_version == TYPE_POWERSAVER) { |
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if (lo & (1<<27)) |
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invalue += 16; |
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} |
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return eblcr[invalue]; |
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} |
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/* For processor with BCR2 MSR */ |
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static void do_longhaul1(unsigned int mults_index) |
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{ |
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union msr_bcr2 bcr2; |
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rdmsrl(MSR_VIA_BCR2, bcr2.val); |
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/* Enable software clock multiplier */ |
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bcr2.bits.ESOFTBF = 1; |
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bcr2.bits.CLOCKMUL = mults_index & 0xff; |
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/* Sync to timer tick */ |
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safe_halt(); |
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/* Change frequency on next halt or sleep */ |
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wrmsrl(MSR_VIA_BCR2, bcr2.val); |
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/* Invoke transition */ |
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ACPI_FLUSH_CPU_CACHE(); |
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halt(); |
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/* Disable software clock multiplier */ |
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local_irq_disable(); |
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rdmsrl(MSR_VIA_BCR2, bcr2.val); |
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bcr2.bits.ESOFTBF = 0; |
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wrmsrl(MSR_VIA_BCR2, bcr2.val); |
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} |
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/* For processor with Longhaul MSR */ |
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static void do_powersaver(int cx_address, unsigned int mults_index, |
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unsigned int dir) |
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{ |
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union msr_longhaul longhaul; |
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u32 t; |
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rdmsrl(MSR_VIA_LONGHAUL, longhaul.val); |
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/* Setup new frequency */ |
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if (!revid_errata) |
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longhaul.bits.RevisionKey = longhaul.bits.RevisionID; |
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else |
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longhaul.bits.RevisionKey = 0; |
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longhaul.bits.SoftBusRatio = mults_index & 0xf; |
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longhaul.bits.SoftBusRatio4 = (mults_index & 0x10) >> 4; |
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/* Setup new voltage */ |
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if (can_scale_voltage) |
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longhaul.bits.SoftVID = (mults_index >> 8) & 0x1f; |
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/* Sync to timer tick */ |
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safe_halt(); |
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/* Raise voltage if necessary */ |
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if (can_scale_voltage && dir) { |
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longhaul.bits.EnableSoftVID = 1; |
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wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); |
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/* Change voltage */ |
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if (!cx_address) { |
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ACPI_FLUSH_CPU_CACHE(); |
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halt(); |
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} else { |
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ACPI_FLUSH_CPU_CACHE(); |
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/* Invoke C3 */ |
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inb(cx_address); |
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/* Dummy op - must do something useless after P_LVL3 |
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* read */ |
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t = inl(acpi_gbl_FADT.xpm_timer_block.address); |
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} |
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longhaul.bits.EnableSoftVID = 0; |
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wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); |
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} |
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/* Change frequency on next halt or sleep */ |
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longhaul.bits.EnableSoftBusRatio = 1; |
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wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); |
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if (!cx_address) { |
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ACPI_FLUSH_CPU_CACHE(); |
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halt(); |
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} else { |
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ACPI_FLUSH_CPU_CACHE(); |
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/* Invoke C3 */ |
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inb(cx_address); |
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/* Dummy op - must do something useless after P_LVL3 read */ |
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t = inl(acpi_gbl_FADT.xpm_timer_block.address); |
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} |
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/* Disable bus ratio bit */ |
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longhaul.bits.EnableSoftBusRatio = 0; |
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wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); |
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/* Reduce voltage if necessary */ |
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if (can_scale_voltage && !dir) { |
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longhaul.bits.EnableSoftVID = 1; |
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wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); |
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/* Change voltage */ |
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if (!cx_address) { |
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ACPI_FLUSH_CPU_CACHE(); |
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halt(); |
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} else { |
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ACPI_FLUSH_CPU_CACHE(); |
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/* Invoke C3 */ |
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inb(cx_address); |
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/* Dummy op - must do something useless after P_LVL3 |
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* read */ |
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t = inl(acpi_gbl_FADT.xpm_timer_block.address); |
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} |
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longhaul.bits.EnableSoftVID = 0; |
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wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); |
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} |
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} |
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/** |
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* longhaul_set_cpu_frequency() |
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* @mults_index : bitpattern of the new multiplier. |
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* |
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* Sets a new clock ratio. |
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*/ |
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static int longhaul_setstate(struct cpufreq_policy *policy, |
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unsigned int table_index) |
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{ |
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unsigned int mults_index; |
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int speed, mult; |
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struct cpufreq_freqs freqs; |
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unsigned long flags; |
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unsigned int pic1_mask, pic2_mask; |
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u16 bm_status = 0; |
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u32 bm_timeout = 1000; |
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unsigned int dir = 0; |
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mults_index = longhaul_table[table_index].driver_data; |
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/* Safety precautions */ |
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mult = mults[mults_index & 0x1f]; |
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if (mult == -1) |
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return -EINVAL; |
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speed = calc_speed(mult); |
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if ((speed > highest_speed) || (speed < lowest_speed)) |
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return -EINVAL; |
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/* Voltage transition before frequency transition? */ |
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if (can_scale_voltage && longhaul_index < table_index) |
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dir = 1; |
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freqs.old = calc_speed(longhaul_get_cpu_mult()); |
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freqs.new = speed; |
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pr_debug("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n", |
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fsb, mult/10, mult%10, print_speed(speed/1000)); |
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retry_loop: |
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preempt_disable(); |
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local_irq_save(flags); |
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pic2_mask = inb(0xA1); |
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pic1_mask = inb(0x21); /* works on C3. save mask. */ |
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outb(0xFF, 0xA1); /* Overkill */ |
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outb(0xFE, 0x21); /* TMR0 only */ |
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/* Wait while PCI bus is busy. */ |
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if (acpi_regs_addr && (longhaul_flags & USE_NORTHBRIDGE |
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|| ((pr != NULL) && pr->flags.bm_control))) { |
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bm_status = inw(acpi_regs_addr); |
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bm_status &= 1 << 4; |
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while (bm_status && bm_timeout) { |
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outw(1 << 4, acpi_regs_addr); |
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bm_timeout--; |
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bm_status = inw(acpi_regs_addr); |
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bm_status &= 1 << 4; |
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} |
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} |
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if (longhaul_flags & USE_NORTHBRIDGE) { |
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/* Disable AGP and PCI arbiters */ |
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outb(3, 0x22); |
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} else if ((pr != NULL) && pr->flags.bm_control) { |
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/* Disable bus master arbitration */ |
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acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1); |
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} |
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switch (longhaul_version) { |
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/* |
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* Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B]) |
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* Software controlled multipliers only. |
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*/ |
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case TYPE_LONGHAUL_V1: |
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do_longhaul1(mults_index); |
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break; |
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/* |
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* Longhaul v2 appears in Samuel2 Steppings 1->7 [C5B] and Ezra [C5C] |
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* |
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* Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N]) |
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* Nehemiah can do FSB scaling too, but this has never been proven |
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* to work in practice. |
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*/ |
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case TYPE_LONGHAUL_V2: |
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case TYPE_POWERSAVER: |
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if (longhaul_flags & USE_ACPI_C3) { |
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/* Don't allow wakeup */ |
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acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 0); |
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do_powersaver(cx->address, mults_index, dir); |
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} else { |
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do_powersaver(0, mults_index, dir); |
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} |
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break; |
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} |
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if (longhaul_flags & USE_NORTHBRIDGE) { |
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/* Enable arbiters */ |
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outb(0, 0x22); |
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} else if ((pr != NULL) && pr->flags.bm_control) { |
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/* Enable bus master arbitration */ |
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acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0); |
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} |
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outb(pic2_mask, 0xA1); /* restore mask */ |
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outb(pic1_mask, 0x21); |
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local_irq_restore(flags); |
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preempt_enable(); |
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freqs.new = calc_speed(longhaul_get_cpu_mult()); |
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/* Check if requested frequency is set. */ |
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if (unlikely(freqs.new != speed)) { |
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pr_info("Failed to set requested frequency!\n"); |
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/* Revision ID = 1 but processor is expecting revision key |
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* equal to 0. Jumpers at the bottom of processor will change |
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* multiplier and FSB, but will not change bits in Longhaul |
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* MSR nor enable voltage scaling. */ |
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if (!revid_errata) { |
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pr_info("Enabling \"Ignore Revision ID\" option\n"); |
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revid_errata = 1; |
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msleep(200); |
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goto retry_loop; |
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} |
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/* Why ACPI C3 sometimes doesn't work is a mystery for me. |
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* But it does happen. Processor is entering ACPI C3 state, |
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* but it doesn't change frequency. I tried poking various |
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* bits in northbridge registers, but without success. */ |
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if (longhaul_flags & USE_ACPI_C3) { |
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pr_info("Disabling ACPI C3 support\n"); |
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longhaul_flags &= ~USE_ACPI_C3; |
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if (revid_errata) { |
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pr_info("Disabling \"Ignore Revision ID\" option\n"); |
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revid_errata = 0; |
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} |
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msleep(200); |
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goto retry_loop; |
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} |
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/* This shouldn't happen. Longhaul ver. 2 was reported not |
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* working on processors without voltage scaling, but with |
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* RevID = 1. RevID errata will make things right. Just |
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* to be 100% sure. */ |
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if (longhaul_version == TYPE_LONGHAUL_V2) { |
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pr_info("Switching to Longhaul ver. 1\n"); |
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longhaul_version = TYPE_LONGHAUL_V1; |
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msleep(200); |
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goto retry_loop; |
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} |
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} |
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if (!bm_timeout) { |
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pr_info("Warning: Timeout while waiting for idle PCI bus\n"); |
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return -EBUSY; |
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} |
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return 0; |
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} |
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/* |
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* Centaur decided to make life a little more tricky. |
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* Only longhaul v1 is allowed to read EBLCR BSEL[0:1]. |
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* Samuel2 and above have to try and guess what the FSB is. |
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* We do this by assuming we booted at maximum multiplier, and interpolate |
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* between that value multiplied by possible FSBs and cpu_mhz which |
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* was calculated at boot time. Really ugly, but no other way to do this. |
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*/ |
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#define ROUNDING 0xf |
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static int guess_fsb(int mult) |
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{ |
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int speed = cpu_khz / 1000; |
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int i; |
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int speeds[] = { 666, 1000, 1333, 2000 }; |
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int f_max, f_min; |
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for (i = 0; i < 4; i++) { |
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f_max = ((speeds[i] * mult) + 50) / 100; |
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f_max += (ROUNDING / 2); |
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f_min = f_max - ROUNDING; |
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if ((speed <= f_max) && (speed >= f_min)) |
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return speeds[i] / 10; |
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} |
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return 0; |
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} |
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static int longhaul_get_ranges(void) |
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{ |
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unsigned int i, j, k = 0; |
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unsigned int ratio; |
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int mult; |
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/* Get current frequency */ |
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mult = longhaul_get_cpu_mult(); |
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if (mult == -1) { |
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pr_info("Invalid (reserved) multiplier!\n"); |
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return -EINVAL; |
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} |
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fsb = guess_fsb(mult); |
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if (fsb == 0) { |
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pr_info("Invalid (reserved) FSB!\n"); |
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return -EINVAL; |
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} |
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/* Get max multiplier - as we always did. |
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* Longhaul MSR is useful only when voltage scaling is enabled. |
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* C3 is booting at max anyway. */ |
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maxmult = mult; |
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/* Get min multiplier */ |
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switch (cpu_model) { |
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case CPU_NEHEMIAH: |
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minmult = 50; |
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break; |
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case CPU_NEHEMIAH_C: |
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minmult = 40; |
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break; |
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default: |
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minmult = 30; |
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break; |
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} |
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pr_debug("MinMult:%d.%dx MaxMult:%d.%dx\n", |
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minmult/10, minmult%10, maxmult/10, maxmult%10); |
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highest_speed = calc_speed(maxmult); |
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lowest_speed = calc_speed(minmult); |
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pr_debug("FSB:%dMHz Lowest speed: %s Highest speed:%s\n", fsb, |
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print_speed(lowest_speed/1000), |
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print_speed(highest_speed/1000)); |
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if (lowest_speed == highest_speed) { |
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pr_info("highestspeed == lowest, aborting\n"); |
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return -EINVAL; |
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} |
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if (lowest_speed > highest_speed) { |
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pr_info("nonsense! lowest (%d > %d) !\n", |
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lowest_speed, highest_speed); |
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return -EINVAL; |
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} |
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longhaul_table = kcalloc(numscales + 1, sizeof(*longhaul_table), |
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GFP_KERNEL); |
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if (!longhaul_table) |
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return -ENOMEM; |
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for (j = 0; j < numscales; j++) { |
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ratio = mults[j]; |
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if (ratio == -1) |
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continue; |
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if (ratio > maxmult || ratio < minmult) |
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continue; |
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longhaul_table[k].frequency = calc_speed(ratio); |
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longhaul_table[k].driver_data = j; |
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k++; |
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} |
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if (k <= 1) { |
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kfree(longhaul_table); |
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return -ENODEV; |
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} |
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/* Sort */ |
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for (j = 0; j < k - 1; j++) { |
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unsigned int min_f, min_i; |
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min_f = longhaul_table[j].frequency; |
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min_i = j; |
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for (i = j + 1; i < k; i++) { |
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if (longhaul_table[i].frequency < min_f) { |
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min_f = longhaul_table[i].frequency; |
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min_i = i; |
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} |
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} |
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if (min_i != j) { |
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swap(longhaul_table[j].frequency, |
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longhaul_table[min_i].frequency); |
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swap(longhaul_table[j].driver_data, |
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longhaul_table[min_i].driver_data); |
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} |
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} |
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longhaul_table[k].frequency = CPUFREQ_TABLE_END; |
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/* Find index we are running on */ |
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for (j = 0; j < k; j++) { |
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if (mults[longhaul_table[j].driver_data & 0x1f] == mult) { |
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longhaul_index = j; |
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break; |
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} |
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} |
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return 0; |
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} |
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static void longhaul_setup_voltagescaling(void) |
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{ |
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struct cpufreq_frequency_table *freq_pos; |
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union msr_longhaul longhaul; |
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struct mV_pos minvid, maxvid, vid; |
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unsigned int j, speed, pos, kHz_step, numvscales; |
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int min_vid_speed; |
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rdmsrl(MSR_VIA_LONGHAUL, longhaul.val); |
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if (!(longhaul.bits.RevisionID & 1)) { |
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pr_info("Voltage scaling not supported by CPU\n"); |
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return; |
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} |
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if (!longhaul.bits.VRMRev) { |
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pr_info("VRM 8.5\n"); |
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vrm_mV_table = &vrm85_mV[0]; |
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mV_vrm_table = &mV_vrm85[0]; |
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} else { |
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pr_info("Mobile VRM\n"); |
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if (cpu_model < CPU_NEHEMIAH) |
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return; |
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vrm_mV_table = &mobilevrm_mV[0]; |
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mV_vrm_table = &mV_mobilevrm[0]; |
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} |
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minvid = vrm_mV_table[longhaul.bits.MinimumVID]; |
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maxvid = vrm_mV_table[longhaul.bits.MaximumVID]; |
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|
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if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) { |
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pr_info("Bogus values Min:%d.%03d Max:%d.%03d - Voltage scaling disabled\n", |
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minvid.mV/1000, minvid.mV%1000, |
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maxvid.mV/1000, maxvid.mV%1000); |
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return; |
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} |
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|
|
if (minvid.mV == maxvid.mV) { |
|
pr_info("Claims to support voltage scaling but min & max are both %d.%03d - Voltage scaling disabled\n", |
|
maxvid.mV/1000, maxvid.mV%1000); |
|
return; |
|
} |
|
|
|
/* How many voltage steps*/ |
|
numvscales = maxvid.pos - minvid.pos + 1; |
|
pr_info("Max VID=%d.%03d Min VID=%d.%03d, %d possible voltage scales\n", |
|
maxvid.mV/1000, maxvid.mV%1000, |
|
minvid.mV/1000, minvid.mV%1000, |
|
numvscales); |
|
|
|
/* Calculate max frequency at min voltage */ |
|
j = longhaul.bits.MinMHzBR; |
|
if (longhaul.bits.MinMHzBR4) |
|
j += 16; |
|
min_vid_speed = eblcr[j]; |
|
if (min_vid_speed == -1) |
|
return; |
|
switch (longhaul.bits.MinMHzFSB) { |
|
case 0: |
|
min_vid_speed *= 13333; |
|
break; |
|
case 1: |
|
min_vid_speed *= 10000; |
|
break; |
|
case 3: |
|
min_vid_speed *= 6666; |
|
break; |
|
default: |
|
return; |
|
} |
|
if (min_vid_speed >= highest_speed) |
|
return; |
|
/* Calculate kHz for one voltage step */ |
|
kHz_step = (highest_speed - min_vid_speed) / numvscales; |
|
|
|
cpufreq_for_each_entry_idx(freq_pos, longhaul_table, j) { |
|
speed = freq_pos->frequency; |
|
if (speed > min_vid_speed) |
|
pos = (speed - min_vid_speed) / kHz_step + minvid.pos; |
|
else |
|
pos = minvid.pos; |
|
freq_pos->driver_data |= mV_vrm_table[pos] << 8; |
|
vid = vrm_mV_table[mV_vrm_table[pos]]; |
|
pr_info("f: %d kHz, index: %d, vid: %d mV\n", |
|
speed, j, vid.mV); |
|
} |
|
|
|
can_scale_voltage = 1; |
|
pr_info("Voltage scaling enabled\n"); |
|
} |
|
|
|
|
|
static int longhaul_target(struct cpufreq_policy *policy, |
|
unsigned int table_index) |
|
{ |
|
unsigned int i; |
|
unsigned int dir = 0; |
|
u8 vid, current_vid; |
|
int retval = 0; |
|
|
|
if (!can_scale_voltage) |
|
retval = longhaul_setstate(policy, table_index); |
|
else { |
|
/* On test system voltage transitions exceeding single |
|
* step up or down were turning motherboard off. Both |
|
* "ondemand" and "userspace" are unsafe. C7 is doing |
|
* this in hardware, C3 is old and we need to do this |
|
* in software. */ |
|
i = longhaul_index; |
|
current_vid = (longhaul_table[longhaul_index].driver_data >> 8); |
|
current_vid &= 0x1f; |
|
if (table_index > longhaul_index) |
|
dir = 1; |
|
while (i != table_index) { |
|
vid = (longhaul_table[i].driver_data >> 8) & 0x1f; |
|
if (vid != current_vid) { |
|
retval = longhaul_setstate(policy, i); |
|
current_vid = vid; |
|
msleep(200); |
|
} |
|
if (dir) |
|
i++; |
|
else |
|
i--; |
|
} |
|
retval = longhaul_setstate(policy, table_index); |
|
} |
|
|
|
longhaul_index = table_index; |
|
return retval; |
|
} |
|
|
|
|
|
static unsigned int longhaul_get(unsigned int cpu) |
|
{ |
|
if (cpu) |
|
return 0; |
|
return calc_speed(longhaul_get_cpu_mult()); |
|
} |
|
|
|
static acpi_status longhaul_walk_callback(acpi_handle obj_handle, |
|
u32 nesting_level, |
|
void *context, void **return_value) |
|
{ |
|
struct acpi_device *d; |
|
|
|
if (acpi_bus_get_device(obj_handle, &d)) |
|
return 0; |
|
|
|
*return_value = acpi_driver_data(d); |
|
return 1; |
|
} |
|
|
|
/* VIA don't support PM2 reg, but have something similar */ |
|
static int enable_arbiter_disable(void) |
|
{ |
|
struct pci_dev *dev; |
|
int status = 1; |
|
int reg; |
|
u8 pci_cmd; |
|
|
|
/* Find PLE133 host bridge */ |
|
reg = 0x78; |
|
dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8601_0, |
|
NULL); |
|
/* Find PM133/VT8605 host bridge */ |
|
if (dev == NULL) |
|
dev = pci_get_device(PCI_VENDOR_ID_VIA, |
|
PCI_DEVICE_ID_VIA_8605_0, NULL); |
|
/* Find CLE266 host bridge */ |
|
if (dev == NULL) { |
|
reg = 0x76; |
|
dev = pci_get_device(PCI_VENDOR_ID_VIA, |
|
PCI_DEVICE_ID_VIA_862X_0, NULL); |
|
/* Find CN400 V-Link host bridge */ |
|
if (dev == NULL) |
|
dev = pci_get_device(PCI_VENDOR_ID_VIA, 0x7259, NULL); |
|
} |
|
if (dev != NULL) { |
|
/* Enable access to port 0x22 */ |
|
pci_read_config_byte(dev, reg, &pci_cmd); |
|
if (!(pci_cmd & 1<<7)) { |
|
pci_cmd |= 1<<7; |
|
pci_write_config_byte(dev, reg, pci_cmd); |
|
pci_read_config_byte(dev, reg, &pci_cmd); |
|
if (!(pci_cmd & 1<<7)) { |
|
pr_err("Can't enable access to port 0x22\n"); |
|
status = 0; |
|
} |
|
} |
|
pci_dev_put(dev); |
|
return status; |
|
} |
|
return 0; |
|
} |
|
|
|
static int longhaul_setup_southbridge(void) |
|
{ |
|
struct pci_dev *dev; |
|
u8 pci_cmd; |
|
|
|
/* Find VT8235 southbridge */ |
|
dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, NULL); |
|
if (dev == NULL) |
|
/* Find VT8237 southbridge */ |
|
dev = pci_get_device(PCI_VENDOR_ID_VIA, |
|
PCI_DEVICE_ID_VIA_8237, NULL); |
|
if (dev != NULL) { |
|
/* Set transition time to max */ |
|
pci_read_config_byte(dev, 0xec, &pci_cmd); |
|
pci_cmd &= ~(1 << 2); |
|
pci_write_config_byte(dev, 0xec, pci_cmd); |
|
pci_read_config_byte(dev, 0xe4, &pci_cmd); |
|
pci_cmd &= ~(1 << 7); |
|
pci_write_config_byte(dev, 0xe4, pci_cmd); |
|
pci_read_config_byte(dev, 0xe5, &pci_cmd); |
|
pci_cmd |= 1 << 7; |
|
pci_write_config_byte(dev, 0xe5, pci_cmd); |
|
/* Get address of ACPI registers block*/ |
|
pci_read_config_byte(dev, 0x81, &pci_cmd); |
|
if (pci_cmd & 1 << 7) { |
|
pci_read_config_dword(dev, 0x88, &acpi_regs_addr); |
|
acpi_regs_addr &= 0xff00; |
|
pr_info("ACPI I/O at 0x%x\n", acpi_regs_addr); |
|
} |
|
|
|
pci_dev_put(dev); |
|
return 1; |
|
} |
|
return 0; |
|
} |
|
|
|
static int longhaul_cpu_init(struct cpufreq_policy *policy) |
|
{ |
|
struct cpuinfo_x86 *c = &cpu_data(0); |
|
char *cpuname = NULL; |
|
int ret; |
|
u32 lo, hi; |
|
|
|
/* Check what we have on this motherboard */ |
|
switch (c->x86_model) { |
|
case 6: |
|
cpu_model = CPU_SAMUEL; |
|
cpuname = "C3 'Samuel' [C5A]"; |
|
longhaul_version = TYPE_LONGHAUL_V1; |
|
memcpy(mults, samuel1_mults, sizeof(samuel1_mults)); |
|
memcpy(eblcr, samuel1_eblcr, sizeof(samuel1_eblcr)); |
|
break; |
|
|
|
case 7: |
|
switch (c->x86_stepping) { |
|
case 0: |
|
longhaul_version = TYPE_LONGHAUL_V1; |
|
cpu_model = CPU_SAMUEL2; |
|
cpuname = "C3 'Samuel 2' [C5B]"; |
|
/* Note, this is not a typo, early Samuel2's had |
|
* Samuel1 ratios. */ |
|
memcpy(mults, samuel1_mults, sizeof(samuel1_mults)); |
|
memcpy(eblcr, samuel2_eblcr, sizeof(samuel2_eblcr)); |
|
break; |
|
case 1 ... 15: |
|
longhaul_version = TYPE_LONGHAUL_V2; |
|
if (c->x86_stepping < 8) { |
|
cpu_model = CPU_SAMUEL2; |
|
cpuname = "C3 'Samuel 2' [C5B]"; |
|
} else { |
|
cpu_model = CPU_EZRA; |
|
cpuname = "C3 'Ezra' [C5C]"; |
|
} |
|
memcpy(mults, ezra_mults, sizeof(ezra_mults)); |
|
memcpy(eblcr, ezra_eblcr, sizeof(ezra_eblcr)); |
|
break; |
|
} |
|
break; |
|
|
|
case 8: |
|
cpu_model = CPU_EZRA_T; |
|
cpuname = "C3 'Ezra-T' [C5M]"; |
|
longhaul_version = TYPE_POWERSAVER; |
|
numscales = 32; |
|
memcpy(mults, ezrat_mults, sizeof(ezrat_mults)); |
|
memcpy(eblcr, ezrat_eblcr, sizeof(ezrat_eblcr)); |
|
break; |
|
|
|
case 9: |
|
longhaul_version = TYPE_POWERSAVER; |
|
numscales = 32; |
|
memcpy(mults, nehemiah_mults, sizeof(nehemiah_mults)); |
|
memcpy(eblcr, nehemiah_eblcr, sizeof(nehemiah_eblcr)); |
|
switch (c->x86_stepping) { |
|
case 0 ... 1: |
|
cpu_model = CPU_NEHEMIAH; |
|
cpuname = "C3 'Nehemiah A' [C5XLOE]"; |
|
break; |
|
case 2 ... 4: |
|
cpu_model = CPU_NEHEMIAH; |
|
cpuname = "C3 'Nehemiah B' [C5XLOH]"; |
|
break; |
|
case 5 ... 15: |
|
cpu_model = CPU_NEHEMIAH_C; |
|
cpuname = "C3 'Nehemiah C' [C5P]"; |
|
break; |
|
} |
|
break; |
|
|
|
default: |
|
cpuname = "Unknown"; |
|
break; |
|
} |
|
/* Check Longhaul ver. 2 */ |
|
if (longhaul_version == TYPE_LONGHAUL_V2) { |
|
rdmsr(MSR_VIA_LONGHAUL, lo, hi); |
|
if (lo == 0 && hi == 0) |
|
/* Looks like MSR isn't present */ |
|
longhaul_version = TYPE_LONGHAUL_V1; |
|
} |
|
|
|
pr_info("VIA %s CPU detected. ", cpuname); |
|
switch (longhaul_version) { |
|
case TYPE_LONGHAUL_V1: |
|
case TYPE_LONGHAUL_V2: |
|
pr_cont("Longhaul v%d supported\n", longhaul_version); |
|
break; |
|
case TYPE_POWERSAVER: |
|
pr_cont("Powersaver supported\n"); |
|
break; |
|
} |
|
|
|
/* Doesn't hurt */ |
|
longhaul_setup_southbridge(); |
|
|
|
/* Find ACPI data for processor */ |
|
acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT, |
|
ACPI_UINT32_MAX, &longhaul_walk_callback, NULL, |
|
NULL, (void *)&pr); |
|
|
|
/* Check ACPI support for C3 state */ |
|
if (pr != NULL && longhaul_version == TYPE_POWERSAVER) { |
|
cx = &pr->power.states[ACPI_STATE_C3]; |
|
if (cx->address > 0 && cx->latency <= 1000) |
|
longhaul_flags |= USE_ACPI_C3; |
|
} |
|
/* Disable if it isn't working */ |
|
if (disable_acpi_c3) |
|
longhaul_flags &= ~USE_ACPI_C3; |
|
/* Check if northbridge is friendly */ |
|
if (enable_arbiter_disable()) |
|
longhaul_flags |= USE_NORTHBRIDGE; |
|
|
|
/* Check ACPI support for bus master arbiter disable */ |
|
if (!(longhaul_flags & USE_ACPI_C3 |
|
|| longhaul_flags & USE_NORTHBRIDGE) |
|
&& ((pr == NULL) || !(pr->flags.bm_control))) { |
|
pr_err("No ACPI support: Unsupported northbridge\n"); |
|
return -ENODEV; |
|
} |
|
|
|
if (longhaul_flags & USE_NORTHBRIDGE) |
|
pr_info("Using northbridge support\n"); |
|
if (longhaul_flags & USE_ACPI_C3) |
|
pr_info("Using ACPI support\n"); |
|
|
|
ret = longhaul_get_ranges(); |
|
if (ret != 0) |
|
return ret; |
|
|
|
if ((longhaul_version != TYPE_LONGHAUL_V1) && (scale_voltage != 0)) |
|
longhaul_setup_voltagescaling(); |
|
|
|
policy->transition_delay_us = 200000; /* usec */ |
|
policy->freq_table = longhaul_table; |
|
|
|
return 0; |
|
} |
|
|
|
static struct cpufreq_driver longhaul_driver = { |
|
.verify = cpufreq_generic_frequency_table_verify, |
|
.target_index = longhaul_target, |
|
.get = longhaul_get, |
|
.init = longhaul_cpu_init, |
|
.name = "longhaul", |
|
.attr = cpufreq_generic_attr, |
|
}; |
|
|
|
static const struct x86_cpu_id longhaul_id[] = { |
|
X86_MATCH_VENDOR_FAM(CENTAUR, 6, NULL), |
|
{} |
|
}; |
|
MODULE_DEVICE_TABLE(x86cpu, longhaul_id); |
|
|
|
static int __init longhaul_init(void) |
|
{ |
|
struct cpuinfo_x86 *c = &cpu_data(0); |
|
|
|
if (!x86_match_cpu(longhaul_id)) |
|
return -ENODEV; |
|
|
|
if (!enable) { |
|
pr_err("Option \"enable\" not set - Aborting\n"); |
|
return -ENODEV; |
|
} |
|
#ifdef CONFIG_SMP |
|
if (num_online_cpus() > 1) { |
|
pr_err("More than 1 CPU detected, longhaul disabled\n"); |
|
return -ENODEV; |
|
} |
|
#endif |
|
#ifdef CONFIG_X86_IO_APIC |
|
if (boot_cpu_has(X86_FEATURE_APIC)) { |
|
pr_err("APIC detected. Longhaul is currently broken in this configuration.\n"); |
|
return -ENODEV; |
|
} |
|
#endif |
|
switch (c->x86_model) { |
|
case 6 ... 9: |
|
return cpufreq_register_driver(&longhaul_driver); |
|
case 10: |
|
pr_err("Use acpi-cpufreq driver for VIA C7\n"); |
|
default: |
|
; |
|
} |
|
|
|
return -ENODEV; |
|
} |
|
|
|
|
|
static void __exit longhaul_exit(void) |
|
{ |
|
struct cpufreq_policy *policy = cpufreq_cpu_get(0); |
|
int i; |
|
|
|
for (i = 0; i < numscales; i++) { |
|
if (mults[i] == maxmult) { |
|
struct cpufreq_freqs freqs; |
|
|
|
freqs.old = policy->cur; |
|
freqs.new = longhaul_table[i].frequency; |
|
freqs.flags = 0; |
|
|
|
cpufreq_freq_transition_begin(policy, &freqs); |
|
longhaul_setstate(policy, i); |
|
cpufreq_freq_transition_end(policy, &freqs, 0); |
|
break; |
|
} |
|
} |
|
|
|
cpufreq_cpu_put(policy); |
|
cpufreq_unregister_driver(&longhaul_driver); |
|
kfree(longhaul_table); |
|
} |
|
|
|
/* Even if BIOS is exporting ACPI C3 state, and it is used |
|
* with success when CPU is idle, this state doesn't |
|
* trigger frequency transition in some cases. */ |
|
module_param(disable_acpi_c3, int, 0644); |
|
MODULE_PARM_DESC(disable_acpi_c3, "Don't use ACPI C3 support"); |
|
/* Change CPU voltage with frequency. Very useful to save |
|
* power, but most VIA C3 processors aren't supporting it. */ |
|
module_param(scale_voltage, int, 0644); |
|
MODULE_PARM_DESC(scale_voltage, "Scale voltage of processor"); |
|
/* Force revision key to 0 for processors which doesn't |
|
* support voltage scaling, but are introducing itself as |
|
* such. */ |
|
module_param(revid_errata, int, 0644); |
|
MODULE_PARM_DESC(revid_errata, "Ignore CPU Revision ID"); |
|
/* By default driver is disabled to prevent incompatible |
|
* system freeze. */ |
|
module_param(enable, int, 0644); |
|
MODULE_PARM_DESC(enable, "Enable driver"); |
|
|
|
MODULE_AUTHOR("Dave Jones"); |
|
MODULE_DESCRIPTION("Longhaul driver for VIA Cyrix processors."); |
|
MODULE_LICENSE("GPL"); |
|
|
|
late_initcall(longhaul_init); |
|
module_exit(longhaul_exit);
|
|
|