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209 lines
4.8 KiB
209 lines
4.8 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2017 Spreadtrum Communications Inc. |
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*/ |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include "timer-of.h" |
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#define TIMER_NAME "sprd_timer" |
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#define TIMER_LOAD_LO 0x0 |
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#define TIMER_LOAD_HI 0x4 |
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#define TIMER_VALUE_LO 0x8 |
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#define TIMER_VALUE_HI 0xc |
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#define TIMER_CTL 0x10 |
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#define TIMER_CTL_PERIOD_MODE BIT(0) |
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#define TIMER_CTL_ENABLE BIT(1) |
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#define TIMER_CTL_64BIT_WIDTH BIT(16) |
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#define TIMER_INT 0x14 |
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#define TIMER_INT_EN BIT(0) |
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#define TIMER_INT_RAW_STS BIT(1) |
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#define TIMER_INT_MASK_STS BIT(2) |
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#define TIMER_INT_CLR BIT(3) |
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#define TIMER_VALUE_SHDW_LO 0x18 |
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#define TIMER_VALUE_SHDW_HI 0x1c |
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#define TIMER_VALUE_LO_MASK GENMASK(31, 0) |
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static void sprd_timer_enable(void __iomem *base, u32 flag) |
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{ |
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u32 val = readl_relaxed(base + TIMER_CTL); |
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val |= TIMER_CTL_ENABLE; |
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if (flag & TIMER_CTL_64BIT_WIDTH) |
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val |= TIMER_CTL_64BIT_WIDTH; |
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else |
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val &= ~TIMER_CTL_64BIT_WIDTH; |
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if (flag & TIMER_CTL_PERIOD_MODE) |
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val |= TIMER_CTL_PERIOD_MODE; |
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else |
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val &= ~TIMER_CTL_PERIOD_MODE; |
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writel_relaxed(val, base + TIMER_CTL); |
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} |
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static void sprd_timer_disable(void __iomem *base) |
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{ |
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u32 val = readl_relaxed(base + TIMER_CTL); |
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val &= ~TIMER_CTL_ENABLE; |
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writel_relaxed(val, base + TIMER_CTL); |
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} |
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static void sprd_timer_update_counter(void __iomem *base, unsigned long cycles) |
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{ |
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writel_relaxed(cycles & TIMER_VALUE_LO_MASK, base + TIMER_LOAD_LO); |
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writel_relaxed(0, base + TIMER_LOAD_HI); |
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} |
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static void sprd_timer_enable_interrupt(void __iomem *base) |
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{ |
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writel_relaxed(TIMER_INT_EN, base + TIMER_INT); |
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} |
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static void sprd_timer_clear_interrupt(void __iomem *base) |
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{ |
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u32 val = readl_relaxed(base + TIMER_INT); |
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val |= TIMER_INT_CLR; |
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writel_relaxed(val, base + TIMER_INT); |
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} |
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static int sprd_timer_set_next_event(unsigned long cycles, |
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struct clock_event_device *ce) |
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{ |
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struct timer_of *to = to_timer_of(ce); |
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sprd_timer_disable(timer_of_base(to)); |
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sprd_timer_update_counter(timer_of_base(to), cycles); |
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sprd_timer_enable(timer_of_base(to), 0); |
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return 0; |
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} |
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static int sprd_timer_set_periodic(struct clock_event_device *ce) |
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{ |
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struct timer_of *to = to_timer_of(ce); |
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sprd_timer_disable(timer_of_base(to)); |
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sprd_timer_update_counter(timer_of_base(to), timer_of_period(to)); |
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sprd_timer_enable(timer_of_base(to), TIMER_CTL_PERIOD_MODE); |
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return 0; |
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} |
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static int sprd_timer_shutdown(struct clock_event_device *ce) |
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{ |
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struct timer_of *to = to_timer_of(ce); |
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sprd_timer_disable(timer_of_base(to)); |
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return 0; |
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} |
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static irqreturn_t sprd_timer_interrupt(int irq, void *dev_id) |
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{ |
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struct clock_event_device *ce = (struct clock_event_device *)dev_id; |
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struct timer_of *to = to_timer_of(ce); |
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sprd_timer_clear_interrupt(timer_of_base(to)); |
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if (clockevent_state_oneshot(ce)) |
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sprd_timer_disable(timer_of_base(to)); |
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ce->event_handler(ce); |
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return IRQ_HANDLED; |
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} |
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static struct timer_of to = { |
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.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK, |
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.clkevt = { |
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.name = TIMER_NAME, |
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.rating = 300, |
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.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_PERIODIC | |
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CLOCK_EVT_FEAT_ONESHOT, |
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.set_state_shutdown = sprd_timer_shutdown, |
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.set_state_periodic = sprd_timer_set_periodic, |
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.set_next_event = sprd_timer_set_next_event, |
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.cpumask = cpu_possible_mask, |
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}, |
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.of_irq = { |
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.handler = sprd_timer_interrupt, |
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.flags = IRQF_TIMER | IRQF_IRQPOLL, |
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}, |
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}; |
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static int __init sprd_timer_init(struct device_node *np) |
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{ |
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int ret; |
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ret = timer_of_init(np, &to); |
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if (ret) |
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return ret; |
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sprd_timer_enable_interrupt(timer_of_base(&to)); |
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clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), |
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1, UINT_MAX); |
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return 0; |
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} |
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static struct timer_of suspend_to = { |
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.flags = TIMER_OF_BASE | TIMER_OF_CLOCK, |
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}; |
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static u64 sprd_suspend_timer_read(struct clocksource *cs) |
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{ |
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return ~(u64)readl_relaxed(timer_of_base(&suspend_to) + |
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TIMER_VALUE_SHDW_LO) & cs->mask; |
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} |
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static int sprd_suspend_timer_enable(struct clocksource *cs) |
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{ |
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sprd_timer_update_counter(timer_of_base(&suspend_to), |
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TIMER_VALUE_LO_MASK); |
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sprd_timer_enable(timer_of_base(&suspend_to), TIMER_CTL_PERIOD_MODE); |
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return 0; |
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} |
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static void sprd_suspend_timer_disable(struct clocksource *cs) |
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{ |
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sprd_timer_disable(timer_of_base(&suspend_to)); |
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} |
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static struct clocksource suspend_clocksource = { |
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.name = "sprd_suspend_timer", |
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.rating = 200, |
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.read = sprd_suspend_timer_read, |
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.enable = sprd_suspend_timer_enable, |
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.disable = sprd_suspend_timer_disable, |
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.mask = CLOCKSOURCE_MASK(32), |
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.flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP, |
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}; |
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static int __init sprd_suspend_timer_init(struct device_node *np) |
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{ |
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int ret; |
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ret = timer_of_init(np, &suspend_to); |
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if (ret) |
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return ret; |
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clocksource_register_hz(&suspend_clocksource, |
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timer_of_rate(&suspend_to)); |
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return 0; |
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} |
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TIMER_OF_DECLARE(sc9860_timer, "sprd,sc9860-timer", sprd_timer_init); |
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TIMER_OF_DECLARE(sc9860_persistent_timer, "sprd,sc9860-suspend-timer", |
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sprd_suspend_timer_init);
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