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155 lines
4.0 KiB
155 lines
4.0 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/sched_clock.h> |
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#include "timer-of.h" |
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#define CLKSRC_OFFSET 0x40 |
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#define TIMER_STATUS 0x00 |
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#define TIMER_VALUE 0x04 |
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#define TIMER_CONTRL 0x10 |
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#define TIMER_CONFIG 0x20 |
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#define TIMER_DIV 0x24 |
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#define TIMER_INI 0x28 |
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#define GX6605S_STATUS_CLR BIT(0) |
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#define GX6605S_CONTRL_RST BIT(0) |
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#define GX6605S_CONTRL_START BIT(1) |
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#define GX6605S_CONFIG_EN BIT(0) |
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#define GX6605S_CONFIG_IRQ_EN BIT(1) |
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static irqreturn_t gx6605s_timer_interrupt(int irq, void *dev) |
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{ |
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struct clock_event_device *ce = dev; |
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void __iomem *base = timer_of_base(to_timer_of(ce)); |
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writel_relaxed(GX6605S_STATUS_CLR, base + TIMER_STATUS); |
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writel_relaxed(0, base + TIMER_INI); |
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ce->event_handler(ce); |
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return IRQ_HANDLED; |
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} |
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static int gx6605s_timer_set_oneshot(struct clock_event_device *ce) |
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{ |
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void __iomem *base = timer_of_base(to_timer_of(ce)); |
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/* reset and stop counter */ |
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writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL); |
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/* enable with irq and start */ |
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writel_relaxed(GX6605S_CONFIG_EN | GX6605S_CONFIG_IRQ_EN, |
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base + TIMER_CONFIG); |
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return 0; |
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} |
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static int gx6605s_timer_set_next_event(unsigned long delta, |
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struct clock_event_device *ce) |
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{ |
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void __iomem *base = timer_of_base(to_timer_of(ce)); |
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/* use reset to pause timer */ |
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writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL); |
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/* config next timeout value */ |
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writel_relaxed(ULONG_MAX - delta, base + TIMER_INI); |
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writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL); |
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return 0; |
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} |
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static int gx6605s_timer_shutdown(struct clock_event_device *ce) |
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{ |
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void __iomem *base = timer_of_base(to_timer_of(ce)); |
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writel_relaxed(0, base + TIMER_CONTRL); |
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writel_relaxed(0, base + TIMER_CONFIG); |
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return 0; |
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} |
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static struct timer_of to = { |
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.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK, |
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.clkevt = { |
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.rating = 300, |
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.features = CLOCK_EVT_FEAT_DYNIRQ | |
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CLOCK_EVT_FEAT_ONESHOT, |
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.set_state_shutdown = gx6605s_timer_shutdown, |
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.set_state_oneshot = gx6605s_timer_set_oneshot, |
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.set_next_event = gx6605s_timer_set_next_event, |
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.cpumask = cpu_possible_mask, |
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}, |
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.of_irq = { |
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.handler = gx6605s_timer_interrupt, |
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.flags = IRQF_TIMER | IRQF_IRQPOLL, |
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}, |
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}; |
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static u64 notrace gx6605s_sched_clock_read(void) |
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{ |
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void __iomem *base; |
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base = timer_of_base(&to) + CLKSRC_OFFSET; |
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return (u64)readl_relaxed(base + TIMER_VALUE); |
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} |
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static void gx6605s_clkevt_init(void __iomem *base) |
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{ |
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writel_relaxed(0, base + TIMER_DIV); |
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writel_relaxed(0, base + TIMER_CONFIG); |
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clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), 2, |
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ULONG_MAX); |
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} |
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static int gx6605s_clksrc_init(void __iomem *base) |
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{ |
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writel_relaxed(0, base + TIMER_DIV); |
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writel_relaxed(0, base + TIMER_INI); |
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writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL); |
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writel_relaxed(GX6605S_CONFIG_EN, base + TIMER_CONFIG); |
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writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL); |
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sched_clock_register(gx6605s_sched_clock_read, 32, timer_of_rate(&to)); |
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return clocksource_mmio_init(base + TIMER_VALUE, "gx6605s", |
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timer_of_rate(&to), 200, 32, clocksource_mmio_readl_up); |
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} |
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static int __init gx6605s_timer_init(struct device_node *np) |
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{ |
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int ret; |
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/* |
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* The timer driver is for nationalchip gx6605s SOC and there are two |
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* same timer in gx6605s. We use one for clkevt and another for clksrc. |
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* |
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* The timer is mmio map to access, so we need give mmio address in dts. |
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* |
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* It provides a 32bit countup timer and interrupt will be caused by |
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* count-overflow. |
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* So we need set-next-event by ULONG_MAX - delta in TIMER_INI reg. |
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* |
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* The counter at 0x0 offset is clock event. |
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* The counter at 0x40 offset is clock source. |
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* They are the same in hardware, just different used by driver. |
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*/ |
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ret = timer_of_init(np, &to); |
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if (ret) |
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return ret; |
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gx6605s_clkevt_init(timer_of_base(&to)); |
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return gx6605s_clksrc_init(timer_of_base(&to) + CLKSRC_OFFSET); |
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} |
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TIMER_OF_DECLARE(csky_gx6605s_timer, "csky,gx6605s-timer", gx6605s_timer_init);
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