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269 lines
6.4 KiB
269 lines
6.4 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// |
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// Spreadtrum pll clock driver |
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// |
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// Copyright (C) 2015~2017 Spreadtrum, Inc. |
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// Author: Chunyan Zhang <[email protected]> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/regmap.h> |
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#include <linux/slab.h> |
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#include "pll.h" |
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#define CLK_PLL_1M 1000000 |
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#define CLK_PLL_10M (CLK_PLL_1M * 10) |
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#define pindex(pll, member) \ |
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(pll->factors[member].shift / (8 * sizeof(pll->regs_num))) |
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#define pshift(pll, member) \ |
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(pll->factors[member].shift % (8 * sizeof(pll->regs_num))) |
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#define pwidth(pll, member) \ |
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pll->factors[member].width |
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#define pmask(pll, member) \ |
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((pwidth(pll, member)) ? \ |
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GENMASK(pwidth(pll, member) + pshift(pll, member) - 1, \ |
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pshift(pll, member)) : 0) |
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#define pinternal(pll, cfg, member) \ |
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(cfg[pindex(pll, member)] & pmask(pll, member)) |
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#define pinternal_val(pll, cfg, member) \ |
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(pinternal(pll, cfg, member) >> pshift(pll, member)) |
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static inline unsigned int |
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sprd_pll_read(const struct sprd_pll *pll, u8 index) |
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{ |
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const struct sprd_clk_common *common = &pll->common; |
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unsigned int val = 0; |
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if (WARN_ON(index >= pll->regs_num)) |
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return 0; |
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regmap_read(common->regmap, common->reg + index * 4, &val); |
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return val; |
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} |
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static inline void |
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sprd_pll_write(const struct sprd_pll *pll, u8 index, |
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u32 msk, u32 val) |
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{ |
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const struct sprd_clk_common *common = &pll->common; |
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unsigned int offset, reg; |
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int ret = 0; |
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if (WARN_ON(index >= pll->regs_num)) |
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return; |
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offset = common->reg + index * 4; |
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ret = regmap_read(common->regmap, offset, ®); |
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if (!ret) |
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regmap_write(common->regmap, offset, (reg & ~msk) | val); |
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} |
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static unsigned long pll_get_refin(const struct sprd_pll *pll) |
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{ |
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u32 shift, mask, index, refin_id = 3; |
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const unsigned long refin[4] = { 2, 4, 13, 26 }; |
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if (pwidth(pll, PLL_REFIN)) { |
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index = pindex(pll, PLL_REFIN); |
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shift = pshift(pll, PLL_REFIN); |
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mask = pmask(pll, PLL_REFIN); |
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refin_id = (sprd_pll_read(pll, index) & mask) >> shift; |
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if (refin_id > 3) |
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refin_id = 3; |
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} |
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return refin[refin_id]; |
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} |
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static u32 pll_get_ibias(u64 rate, const u64 *table) |
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{ |
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u32 i, num = table[0]; |
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/* table[0] indicates the number of items in this table */ |
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for (i = 0; i < num; i++) |
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if (rate <= table[i + 1]) |
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break; |
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return i == num ? num - 1 : i; |
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} |
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static unsigned long _sprd_pll_recalc_rate(const struct sprd_pll *pll, |
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unsigned long parent_rate) |
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{ |
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u32 *cfg; |
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u32 i, mask, regs_num = pll->regs_num; |
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unsigned long rate, nint, kint = 0; |
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u64 refin; |
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u16 k1, k2; |
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cfg = kcalloc(regs_num, sizeof(*cfg), GFP_KERNEL); |
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if (!cfg) |
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return parent_rate; |
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for (i = 0; i < regs_num; i++) |
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cfg[i] = sprd_pll_read(pll, i); |
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refin = pll_get_refin(pll); |
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if (pinternal(pll, cfg, PLL_PREDIV)) |
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refin = refin * 2; |
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if (pwidth(pll, PLL_POSTDIV) && |
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((pll->fflag == 1 && pinternal(pll, cfg, PLL_POSTDIV)) || |
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(!pll->fflag && !pinternal(pll, cfg, PLL_POSTDIV)))) |
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refin = refin / 2; |
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if (!pinternal(pll, cfg, PLL_DIV_S)) { |
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rate = refin * pinternal_val(pll, cfg, PLL_N) * CLK_PLL_10M; |
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} else { |
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nint = pinternal_val(pll, cfg, PLL_NINT); |
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if (pinternal(pll, cfg, PLL_SDM_EN)) |
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kint = pinternal_val(pll, cfg, PLL_KINT); |
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mask = pmask(pll, PLL_KINT); |
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k1 = pll->k1; |
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k2 = pll->k2; |
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rate = DIV_ROUND_CLOSEST_ULL(refin * kint * k1, |
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((mask >> __ffs(mask)) + 1)) * |
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k2 + refin * nint * CLK_PLL_1M; |
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} |
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kfree(cfg); |
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return rate; |
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} |
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#define SPRD_PLL_WRITE_CHECK(pll, i, mask, val) \ |
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(((sprd_pll_read(pll, i) & mask) == val) ? 0 : (-EFAULT)) |
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static int _sprd_pll_set_rate(const struct sprd_pll *pll, |
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unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct reg_cfg *cfg; |
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int ret = 0; |
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u32 mask, shift, width, ibias_val, index; |
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u32 regs_num = pll->regs_num, i = 0; |
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unsigned long kint, nint; |
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u64 tmp, refin, fvco = rate; |
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cfg = kcalloc(regs_num, sizeof(*cfg), GFP_KERNEL); |
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if (!cfg) |
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return -ENOMEM; |
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refin = pll_get_refin(pll); |
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mask = pmask(pll, PLL_PREDIV); |
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index = pindex(pll, PLL_PREDIV); |
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width = pwidth(pll, PLL_PREDIV); |
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if (width && (sprd_pll_read(pll, index) & mask)) |
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refin = refin * 2; |
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mask = pmask(pll, PLL_POSTDIV); |
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index = pindex(pll, PLL_POSTDIV); |
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width = pwidth(pll, PLL_POSTDIV); |
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cfg[index].msk = mask; |
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if (width && ((pll->fflag == 1 && fvco <= pll->fvco) || |
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(pll->fflag == 0 && fvco > pll->fvco))) |
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cfg[index].val |= mask; |
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if (width && fvco <= pll->fvco) |
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fvco = fvco * 2; |
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mask = pmask(pll, PLL_DIV_S); |
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index = pindex(pll, PLL_DIV_S); |
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cfg[index].val |= mask; |
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cfg[index].msk |= mask; |
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mask = pmask(pll, PLL_SDM_EN); |
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index = pindex(pll, PLL_SDM_EN); |
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cfg[index].val |= mask; |
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cfg[index].msk |= mask; |
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nint = do_div(fvco, refin * CLK_PLL_1M); |
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mask = pmask(pll, PLL_NINT); |
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index = pindex(pll, PLL_NINT); |
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shift = pshift(pll, PLL_NINT); |
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cfg[index].val |= (nint << shift) & mask; |
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cfg[index].msk |= mask; |
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mask = pmask(pll, PLL_KINT); |
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index = pindex(pll, PLL_KINT); |
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width = pwidth(pll, PLL_KINT); |
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shift = pshift(pll, PLL_KINT); |
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tmp = fvco - refin * nint * CLK_PLL_1M; |
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tmp = do_div(tmp, 10000) * ((mask >> shift) + 1); |
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kint = DIV_ROUND_CLOSEST_ULL(tmp, refin * 100); |
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cfg[index].val |= (kint << shift) & mask; |
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cfg[index].msk |= mask; |
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ibias_val = pll_get_ibias(fvco, pll->itable); |
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mask = pmask(pll, PLL_IBIAS); |
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index = pindex(pll, PLL_IBIAS); |
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shift = pshift(pll, PLL_IBIAS); |
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cfg[index].val |= ibias_val << shift & mask; |
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cfg[index].msk |= mask; |
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for (i = 0; i < regs_num; i++) { |
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if (cfg[i].msk) { |
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sprd_pll_write(pll, i, cfg[i].msk, cfg[i].val); |
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ret |= SPRD_PLL_WRITE_CHECK(pll, i, cfg[i].msk, |
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cfg[i].val); |
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} |
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} |
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if (!ret) |
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udelay(pll->udelay); |
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kfree(cfg); |
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return ret; |
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} |
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static unsigned long sprd_pll_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct sprd_pll *pll = hw_to_sprd_pll(hw); |
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return _sprd_pll_recalc_rate(pll, parent_rate); |
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} |
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static int sprd_pll_set_rate(struct clk_hw *hw, |
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unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct sprd_pll *pll = hw_to_sprd_pll(hw); |
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return _sprd_pll_set_rate(pll, rate, parent_rate); |
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} |
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static int sprd_pll_clk_prepare(struct clk_hw *hw) |
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{ |
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struct sprd_pll *pll = hw_to_sprd_pll(hw); |
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udelay(pll->udelay); |
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return 0; |
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} |
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static long sprd_pll_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *prate) |
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{ |
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return rate; |
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} |
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const struct clk_ops sprd_pll_ops = { |
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.prepare = sprd_pll_clk_prepare, |
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.recalc_rate = sprd_pll_recalc_rate, |
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.round_rate = sprd_pll_round_rate, |
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.set_rate = sprd_pll_set_rate, |
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}; |
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EXPORT_SYMBOL_GPL(sprd_pll_ops);
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