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244 lines
6.4 KiB
244 lines
6.4 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Marvell PXA family clocks |
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* |
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* Copyright (C) 2014 Robert Jarzmik |
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* |
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* Common clock code for PXA clocks ("CKEN" type clocks + DT) |
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*/ |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/clkdev.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <dt-bindings/clock/pxa-clock.h> |
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#include "clk-pxa.h" |
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#define KHz 1000 |
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#define MHz (1000 * 1000) |
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#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ |
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#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ |
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#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ |
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#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ |
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#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ |
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#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ |
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#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ |
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#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ |
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#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ |
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#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ |
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#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ |
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#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ |
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#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ |
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#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ |
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#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2) |
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#define MDREFR_DRI_MASK 0xFFF |
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static DEFINE_SPINLOCK(pxa_clk_lock); |
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static struct clk *pxa_clocks[CLK_MAX]; |
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static struct clk_onecell_data onecell_data = { |
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.clks = pxa_clocks, |
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.clk_num = CLK_MAX, |
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}; |
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struct pxa_clk { |
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struct clk_hw hw; |
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struct clk_fixed_factor lp; |
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struct clk_fixed_factor hp; |
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struct clk_gate gate; |
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bool (*is_in_low_power)(void); |
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}; |
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#define to_pxa_clk(_hw) container_of(_hw, struct pxa_clk, hw) |
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static unsigned long cken_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct pxa_clk *pclk = to_pxa_clk(hw); |
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struct clk_fixed_factor *fix; |
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if (!pclk->is_in_low_power || pclk->is_in_low_power()) |
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fix = &pclk->lp; |
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else |
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fix = &pclk->hp; |
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__clk_hw_set_clk(&fix->hw, hw); |
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return clk_fixed_factor_ops.recalc_rate(&fix->hw, parent_rate); |
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} |
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static const struct clk_ops cken_rate_ops = { |
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.recalc_rate = cken_recalc_rate, |
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}; |
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static u8 cken_get_parent(struct clk_hw *hw) |
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{ |
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struct pxa_clk *pclk = to_pxa_clk(hw); |
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if (!pclk->is_in_low_power) |
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return 0; |
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return pclk->is_in_low_power() ? 0 : 1; |
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} |
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static const struct clk_ops cken_mux_ops = { |
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.get_parent = cken_get_parent, |
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.set_parent = dummy_clk_set_parent, |
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}; |
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void __init clkdev_pxa_register(int ckid, const char *con_id, |
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const char *dev_id, struct clk *clk) |
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{ |
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if (!IS_ERR(clk) && (ckid != CLK_NONE)) |
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pxa_clocks[ckid] = clk; |
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if (!IS_ERR(clk)) |
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clk_register_clkdev(clk, con_id, dev_id); |
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} |
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int __init clk_pxa_cken_init(const struct desc_clk_cken *clks, int nb_clks) |
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{ |
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int i; |
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struct pxa_clk *pxa_clk; |
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struct clk *clk; |
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for (i = 0; i < nb_clks; i++) { |
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pxa_clk = kzalloc(sizeof(*pxa_clk), GFP_KERNEL); |
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pxa_clk->is_in_low_power = clks[i].is_in_low_power; |
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pxa_clk->lp = clks[i].lp; |
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pxa_clk->hp = clks[i].hp; |
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pxa_clk->gate = clks[i].gate; |
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pxa_clk->gate.lock = &pxa_clk_lock; |
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clk = clk_register_composite(NULL, clks[i].name, |
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clks[i].parent_names, 2, |
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&pxa_clk->hw, &cken_mux_ops, |
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&pxa_clk->hw, &cken_rate_ops, |
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&pxa_clk->gate.hw, &clk_gate_ops, |
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clks[i].flags); |
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clkdev_pxa_register(clks[i].ckid, clks[i].con_id, |
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clks[i].dev_id, clk); |
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} |
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return 0; |
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} |
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void __init clk_pxa_dt_common_init(struct device_node *np) |
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{ |
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of_clk_add_provider(np, of_clk_src_onecell_get, &onecell_data); |
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} |
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void pxa2xx_core_turbo_switch(bool on) |
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{ |
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unsigned long flags; |
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unsigned int unused, clkcfg; |
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local_irq_save(flags); |
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asm("mrc p14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); |
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clkcfg &= ~CLKCFG_TURBO & ~CLKCFG_HALFTURBO; |
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if (on) |
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clkcfg |= CLKCFG_TURBO; |
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clkcfg |= CLKCFG_FCS; |
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asm volatile( |
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" b 2f\n" |
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" .align 5\n" |
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"1: mcr p14, 0, %1, c6, c0, 0\n" |
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" b 3f\n" |
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"2: b 1b\n" |
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"3: nop\n" |
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: "=&r" (unused) : "r" (clkcfg)); |
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local_irq_restore(flags); |
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} |
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void pxa2xx_cpll_change(struct pxa2xx_freq *freq, |
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u32 (*mdrefr_dri)(unsigned int), void __iomem *mdrefr, |
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void __iomem *cccr) |
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{ |
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unsigned int clkcfg = freq->clkcfg; |
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unsigned int unused, preset_mdrefr, postset_mdrefr; |
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unsigned long flags; |
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local_irq_save(flags); |
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/* Calculate the next MDREFR. If we're slowing down the SDRAM clock |
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* we need to preset the smaller DRI before the change. If we're |
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* speeding up we need to set the larger DRI value after the change. |
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*/ |
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preset_mdrefr = postset_mdrefr = readl(mdrefr); |
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if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(freq->membus_khz)) { |
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preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK); |
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preset_mdrefr |= mdrefr_dri(freq->membus_khz); |
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} |
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postset_mdrefr = |
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(postset_mdrefr & ~MDREFR_DRI_MASK) | |
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mdrefr_dri(freq->membus_khz); |
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/* If we're dividing the memory clock by two for the SDRAM clock, this |
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* must be set prior to the change. Clearing the divide must be done |
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* after the change. |
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*/ |
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if (freq->div2) { |
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preset_mdrefr |= MDREFR_DB2_MASK; |
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postset_mdrefr |= MDREFR_DB2_MASK; |
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} else { |
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postset_mdrefr &= ~MDREFR_DB2_MASK; |
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} |
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/* Set new the CCCR and prepare CLKCFG */ |
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writel(freq->cccr, cccr); |
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asm volatile( |
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" ldr r4, [%1]\n" |
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" b 2f\n" |
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" .align 5\n" |
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"1: str %3, [%1] /* preset the MDREFR */\n" |
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" mcr p14, 0, %2, c6, c0, 0 /* set CLKCFG[FCS] */\n" |
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" str %4, [%1] /* postset the MDREFR */\n" |
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" b 3f\n" |
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"2: b 1b\n" |
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"3: nop\n" |
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: "=&r" (unused) |
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: "r" (mdrefr), "r" (clkcfg), "r" (preset_mdrefr), |
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"r" (postset_mdrefr) |
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: "r4", "r5"); |
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local_irq_restore(flags); |
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} |
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int pxa2xx_determine_rate(struct clk_rate_request *req, |
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struct pxa2xx_freq *freqs, int nb_freqs) |
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{ |
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int i, closest_below = -1, closest_above = -1; |
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unsigned long rate; |
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for (i = 0; i < nb_freqs; i++) { |
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rate = freqs[i].cpll; |
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if (rate == req->rate) |
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break; |
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if (rate < req->min_rate) |
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continue; |
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if (rate > req->max_rate) |
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continue; |
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if (rate <= req->rate) |
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closest_below = i; |
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if ((rate >= req->rate) && (closest_above == -1)) |
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closest_above = i; |
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} |
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req->best_parent_hw = NULL; |
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if (i < nb_freqs) { |
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rate = req->rate; |
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} else if (closest_below >= 0) { |
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rate = freqs[closest_below].cpll; |
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} else if (closest_above >= 0) { |
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rate = freqs[closest_above].cpll; |
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} else { |
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pr_debug("%s(rate=%lu) no match\n", __func__, req->rate); |
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return -EINVAL; |
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} |
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pr_debug("%s(rate=%lu) rate=%lu\n", __func__, req->rate, rate); |
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req->rate = rate; |
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return 0; |
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}
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