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157 lines
3.9 KiB
157 lines
3.9 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* Hisilicon Hi3620 clock gate driver |
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* |
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* Copyright (c) 2012-2013 Hisilicon Limited. |
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* Copyright (c) 2012-2013 Linaro Limited. |
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* |
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* Author: Haojian Zhuang <[email protected]> |
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* Xin Li <[email protected]> |
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*/ |
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#ifndef __HISI_CLK_H |
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#define __HISI_CLK_H |
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#include <linux/clk-provider.h> |
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#include <linux/io.h> |
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#include <linux/spinlock.h> |
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struct platform_device; |
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struct hisi_clock_data { |
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struct clk_onecell_data clk_data; |
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void __iomem *base; |
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}; |
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struct hisi_fixed_rate_clock { |
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unsigned int id; |
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char *name; |
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const char *parent_name; |
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unsigned long flags; |
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unsigned long fixed_rate; |
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}; |
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struct hisi_fixed_factor_clock { |
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unsigned int id; |
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char *name; |
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const char *parent_name; |
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unsigned long mult; |
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unsigned long div; |
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unsigned long flags; |
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}; |
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struct hisi_mux_clock { |
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unsigned int id; |
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const char *name; |
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const char *const *parent_names; |
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u8 num_parents; |
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unsigned long flags; |
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unsigned long offset; |
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u8 shift; |
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u8 width; |
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u8 mux_flags; |
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u32 *table; |
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const char *alias; |
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}; |
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struct hisi_phase_clock { |
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unsigned int id; |
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const char *name; |
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const char *parent_names; |
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unsigned long flags; |
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unsigned long offset; |
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u8 shift; |
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u8 width; |
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u32 *phase_degrees; |
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u32 *phase_regvals; |
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u8 phase_num; |
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}; |
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struct hisi_divider_clock { |
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unsigned int id; |
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const char *name; |
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const char *parent_name; |
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unsigned long flags; |
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unsigned long offset; |
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u8 shift; |
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u8 width; |
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u8 div_flags; |
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struct clk_div_table *table; |
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const char *alias; |
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}; |
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struct hi6220_divider_clock { |
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unsigned int id; |
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const char *name; |
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const char *parent_name; |
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unsigned long flags; |
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unsigned long offset; |
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u8 shift; |
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u8 width; |
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u32 mask_bit; |
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const char *alias; |
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}; |
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struct hisi_gate_clock { |
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unsigned int id; |
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const char *name; |
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const char *parent_name; |
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unsigned long flags; |
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unsigned long offset; |
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u8 bit_idx; |
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u8 gate_flags; |
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const char *alias; |
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}; |
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struct clk *hisi_register_clkgate_sep(struct device *, const char *, |
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const char *, unsigned long, |
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void __iomem *, u8, |
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u8, spinlock_t *); |
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struct clk *hi6220_register_clkdiv(struct device *dev, const char *name, |
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const char *parent_name, unsigned long flags, void __iomem *reg, |
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u8 shift, u8 width, u32 mask_bit, spinlock_t *lock); |
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struct hisi_clock_data *hisi_clk_alloc(struct platform_device *, int); |
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struct hisi_clock_data *hisi_clk_init(struct device_node *, int); |
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int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *, |
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int, struct hisi_clock_data *); |
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int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *, |
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int, struct hisi_clock_data *); |
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int hisi_clk_register_mux(const struct hisi_mux_clock *, int, |
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struct hisi_clock_data *); |
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struct clk *clk_register_hisi_phase(struct device *dev, |
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const struct hisi_phase_clock *clks, |
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void __iomem *base, spinlock_t *lock); |
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int hisi_clk_register_phase(struct device *dev, |
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const struct hisi_phase_clock *clks, |
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int nums, struct hisi_clock_data *data); |
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int hisi_clk_register_divider(const struct hisi_divider_clock *, |
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int, struct hisi_clock_data *); |
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int hisi_clk_register_gate(const struct hisi_gate_clock *, |
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int, struct hisi_clock_data *); |
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void hisi_clk_register_gate_sep(const struct hisi_gate_clock *, |
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int, struct hisi_clock_data *); |
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void hi6220_clk_register_divider(const struct hi6220_divider_clock *, |
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int, struct hisi_clock_data *); |
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#define hisi_clk_unregister(type) \ |
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static inline \ |
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void hisi_clk_unregister_##type(const struct hisi_##type##_clock *clks, \ |
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int nums, struct hisi_clock_data *data) \ |
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{ \ |
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struct clk **clocks = data->clk_data.clks; \ |
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int i; \ |
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for (i = 0; i < nums; i++) { \ |
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int id = clks[i].id; \ |
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if (clocks[id]) \ |
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clk_unregister_##type(clocks[id]); \ |
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} \ |
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} |
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hisi_clk_unregister(fixed_rate) |
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hisi_clk_unregister(fixed_factor) |
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hisi_clk_unregister(mux) |
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hisi_clk_unregister(divider) |
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hisi_clk_unregister(gate) |
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#endif /* __HISI_CLK_H */
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