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302 lines
7.5 KiB
302 lines
7.5 KiB
/* |
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* Clock driver for Palmas device. |
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* |
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* Copyright (c) 2013, NVIDIA Corporation. |
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* Copyright (c) 2013-2014 Texas Instruments, Inc. |
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* |
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* Author: Laxman Dewangan <[email protected]> |
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* Peter Ujfalusi <[email protected]> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation version 2. |
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* |
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, |
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* whether express or implied; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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* General Public License for more details. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/mfd/palmas.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#define PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE1 1 |
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#define PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE2 2 |
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#define PALMAS_CLOCK_DT_EXT_CONTROL_NSLEEP 3 |
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struct palmas_clk32k_desc { |
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const char *clk_name; |
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unsigned int control_reg; |
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unsigned int enable_mask; |
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unsigned int sleep_mask; |
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unsigned int sleep_reqstr_id; |
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int delay; |
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}; |
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struct palmas_clock_info { |
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struct device *dev; |
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struct clk_hw hw; |
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struct palmas *palmas; |
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const struct palmas_clk32k_desc *clk_desc; |
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int ext_control_pin; |
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}; |
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static inline struct palmas_clock_info *to_palmas_clks_info(struct clk_hw *hw) |
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{ |
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return container_of(hw, struct palmas_clock_info, hw); |
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} |
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static unsigned long palmas_clks_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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return 32768; |
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} |
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static int palmas_clks_prepare(struct clk_hw *hw) |
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{ |
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struct palmas_clock_info *cinfo = to_palmas_clks_info(hw); |
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int ret; |
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ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE, |
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cinfo->clk_desc->control_reg, |
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cinfo->clk_desc->enable_mask, |
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cinfo->clk_desc->enable_mask); |
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if (ret < 0) |
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dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n", |
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cinfo->clk_desc->control_reg, ret); |
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else if (cinfo->clk_desc->delay) |
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udelay(cinfo->clk_desc->delay); |
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return ret; |
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} |
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static void palmas_clks_unprepare(struct clk_hw *hw) |
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{ |
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struct palmas_clock_info *cinfo = to_palmas_clks_info(hw); |
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int ret; |
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/* |
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* Clock can be disabled through external pin if it is externally |
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* controlled. |
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*/ |
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if (cinfo->ext_control_pin) |
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return; |
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ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE, |
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cinfo->clk_desc->control_reg, |
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cinfo->clk_desc->enable_mask, 0); |
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if (ret < 0) |
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dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n", |
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cinfo->clk_desc->control_reg, ret); |
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} |
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static int palmas_clks_is_prepared(struct clk_hw *hw) |
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{ |
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struct palmas_clock_info *cinfo = to_palmas_clks_info(hw); |
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int ret; |
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u32 val; |
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if (cinfo->ext_control_pin) |
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return 1; |
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ret = palmas_read(cinfo->palmas, PALMAS_RESOURCE_BASE, |
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cinfo->clk_desc->control_reg, &val); |
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if (ret < 0) { |
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dev_err(cinfo->dev, "Reg 0x%02x read failed, %d\n", |
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cinfo->clk_desc->control_reg, ret); |
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return ret; |
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} |
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return !!(val & cinfo->clk_desc->enable_mask); |
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} |
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static const struct clk_ops palmas_clks_ops = { |
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.prepare = palmas_clks_prepare, |
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.unprepare = palmas_clks_unprepare, |
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.is_prepared = palmas_clks_is_prepared, |
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.recalc_rate = palmas_clks_recalc_rate, |
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}; |
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struct palmas_clks_of_match_data { |
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struct clk_init_data init; |
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const struct palmas_clk32k_desc desc; |
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}; |
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static const struct palmas_clks_of_match_data palmas_of_clk32kg = { |
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.init = { |
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.name = "clk32kg", |
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.ops = &palmas_clks_ops, |
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.flags = CLK_IGNORE_UNUSED, |
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}, |
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.desc = { |
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.clk_name = "clk32kg", |
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.control_reg = PALMAS_CLK32KG_CTRL, |
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.enable_mask = PALMAS_CLK32KG_CTRL_MODE_ACTIVE, |
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.sleep_mask = PALMAS_CLK32KG_CTRL_MODE_SLEEP, |
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.sleep_reqstr_id = PALMAS_EXTERNAL_REQSTR_ID_CLK32KG, |
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.delay = 200, |
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}, |
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}; |
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static const struct palmas_clks_of_match_data palmas_of_clk32kgaudio = { |
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.init = { |
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.name = "clk32kgaudio", |
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.ops = &palmas_clks_ops, |
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.flags = CLK_IGNORE_UNUSED, |
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}, |
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.desc = { |
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.clk_name = "clk32kgaudio", |
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.control_reg = PALMAS_CLK32KGAUDIO_CTRL, |
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.enable_mask = PALMAS_CLK32KG_CTRL_MODE_ACTIVE, |
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.sleep_mask = PALMAS_CLK32KG_CTRL_MODE_SLEEP, |
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.sleep_reqstr_id = PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO, |
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.delay = 200, |
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}, |
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}; |
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static const struct of_device_id palmas_clks_of_match[] = { |
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{ |
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.compatible = "ti,palmas-clk32kg", |
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.data = &palmas_of_clk32kg, |
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}, |
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{ |
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.compatible = "ti,palmas-clk32kgaudio", |
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.data = &palmas_of_clk32kgaudio, |
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}, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, palmas_clks_of_match); |
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static void palmas_clks_get_clk_data(struct platform_device *pdev, |
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struct palmas_clock_info *cinfo) |
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{ |
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struct device_node *node = pdev->dev.of_node; |
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unsigned int prop; |
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int ret; |
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ret = of_property_read_u32(node, "ti,external-sleep-control", |
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&prop); |
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if (ret) |
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return; |
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switch (prop) { |
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case PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE1: |
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prop = PALMAS_EXT_CONTROL_ENABLE1; |
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break; |
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case PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE2: |
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prop = PALMAS_EXT_CONTROL_ENABLE2; |
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break; |
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case PALMAS_CLOCK_DT_EXT_CONTROL_NSLEEP: |
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prop = PALMAS_EXT_CONTROL_NSLEEP; |
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break; |
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default: |
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dev_warn(&pdev->dev, "%pOFn: Invalid ext control option: %u\n", |
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node, prop); |
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prop = 0; |
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break; |
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} |
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cinfo->ext_control_pin = prop; |
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} |
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static int palmas_clks_init_configure(struct palmas_clock_info *cinfo) |
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{ |
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int ret; |
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ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE, |
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cinfo->clk_desc->control_reg, |
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cinfo->clk_desc->sleep_mask, 0); |
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if (ret < 0) { |
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dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n", |
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cinfo->clk_desc->control_reg, ret); |
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return ret; |
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} |
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if (cinfo->ext_control_pin) { |
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ret = clk_prepare(cinfo->hw.clk); |
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if (ret < 0) { |
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dev_err(cinfo->dev, "Clock prep failed, %d\n", ret); |
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return ret; |
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} |
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ret = palmas_ext_control_req_config(cinfo->palmas, |
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cinfo->clk_desc->sleep_reqstr_id, |
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cinfo->ext_control_pin, true); |
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if (ret < 0) { |
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dev_err(cinfo->dev, "Ext config for %s failed, %d\n", |
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cinfo->clk_desc->clk_name, ret); |
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clk_unprepare(cinfo->hw.clk); |
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return ret; |
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} |
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} |
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return ret; |
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} |
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static int palmas_clks_probe(struct platform_device *pdev) |
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{ |
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struct palmas *palmas = dev_get_drvdata(pdev->dev.parent); |
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struct device_node *node = pdev->dev.of_node; |
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const struct palmas_clks_of_match_data *match_data; |
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struct palmas_clock_info *cinfo; |
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int ret; |
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match_data = of_device_get_match_data(&pdev->dev); |
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if (!match_data) |
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return 1; |
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cinfo = devm_kzalloc(&pdev->dev, sizeof(*cinfo), GFP_KERNEL); |
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if (!cinfo) |
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return -ENOMEM; |
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palmas_clks_get_clk_data(pdev, cinfo); |
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platform_set_drvdata(pdev, cinfo); |
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cinfo->dev = &pdev->dev; |
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cinfo->palmas = palmas; |
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cinfo->clk_desc = &match_data->desc; |
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cinfo->hw.init = &match_data->init; |
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ret = devm_clk_hw_register(&pdev->dev, &cinfo->hw); |
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if (ret) { |
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dev_err(&pdev->dev, "Fail to register clock %s, %d\n", |
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match_data->desc.clk_name, ret); |
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return ret; |
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} |
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ret = palmas_clks_init_configure(cinfo); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "Clock config failed, %d\n", ret); |
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return ret; |
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} |
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ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &cinfo->hw); |
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if (ret < 0) |
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dev_err(&pdev->dev, "Fail to add clock driver, %d\n", ret); |
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return ret; |
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} |
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static int palmas_clks_remove(struct platform_device *pdev) |
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{ |
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of_clk_del_provider(pdev->dev.of_node); |
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return 0; |
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} |
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static struct platform_driver palmas_clks_driver = { |
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.driver = { |
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.name = "palmas-clk", |
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.of_match_table = palmas_clks_of_match, |
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}, |
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.probe = palmas_clks_probe, |
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.remove = palmas_clks_remove, |
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}; |
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module_platform_driver(palmas_clks_driver); |
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MODULE_DESCRIPTION("Clock driver for Palmas Series Devices"); |
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MODULE_ALIAS("platform:palmas-clk"); |
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MODULE_AUTHOR("Peter Ujfalusi <[email protected]>"); |
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MODULE_LICENSE("GPL v2");
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