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60 lines
1.4 KiB
60 lines
1.4 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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// |
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// OWL mux clock driver |
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// |
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// Copyright (c) 2014 Actions Semi Inc. |
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// Author: David Liu <[email protected]> |
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// |
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// Copyright (c) 2018 Linaro Ltd. |
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// Author: Manivannan Sadhasivam <[email protected]> |
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#include <linux/clk-provider.h> |
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#include <linux/regmap.h> |
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#include "owl-mux.h" |
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u8 owl_mux_helper_get_parent(const struct owl_clk_common *common, |
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const struct owl_mux_hw *mux_hw) |
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{ |
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u32 reg; |
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u8 parent; |
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regmap_read(common->regmap, mux_hw->reg, ®); |
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parent = reg >> mux_hw->shift; |
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parent &= BIT(mux_hw->width) - 1; |
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return parent; |
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} |
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static u8 owl_mux_get_parent(struct clk_hw *hw) |
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{ |
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struct owl_mux *mux = hw_to_owl_mux(hw); |
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return owl_mux_helper_get_parent(&mux->common, &mux->mux_hw); |
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} |
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int owl_mux_helper_set_parent(const struct owl_clk_common *common, |
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struct owl_mux_hw *mux_hw, u8 index) |
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{ |
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u32 reg; |
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regmap_read(common->regmap, mux_hw->reg, ®); |
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reg &= ~GENMASK(mux_hw->width + mux_hw->shift - 1, mux_hw->shift); |
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regmap_write(common->regmap, mux_hw->reg, |
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reg | (index << mux_hw->shift)); |
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return 0; |
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} |
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static int owl_mux_set_parent(struct clk_hw *hw, u8 index) |
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{ |
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struct owl_mux *mux = hw_to_owl_mux(hw); |
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return owl_mux_helper_set_parent(&mux->common, &mux->mux_hw, index); |
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} |
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const struct clk_ops owl_mux_ops = { |
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.get_parent = owl_mux_get_parent, |
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.set_parent = owl_mux_set_parent, |
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.determine_rate = __clk_mux_determine_rate, |
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};
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