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406 lines
10 KiB
406 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Qualcomm External Bus Interface 2 (EBI2) driver |
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* an older version of the Qualcomm Parallel Interface Controller (QPIC) |
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* |
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* Copyright (C) 2016 Linaro Ltd. |
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* |
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* Author: Linus Walleij <[email protected]> |
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* |
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* See the device tree bindings for this block for more details on the |
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* hardware. |
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*/ |
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#include <linux/module.h> |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_platform.h> |
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#include <linux/init.h> |
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#include <linux/slab.h> |
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#include <linux/platform_device.h> |
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#include <linux/bitops.h> |
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/* |
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* CS0, CS1, CS4 and CS5 are two bits wide, CS2 and CS3 are one bit. |
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*/ |
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#define EBI2_CS0_ENABLE_MASK BIT(0)|BIT(1) |
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#define EBI2_CS1_ENABLE_MASK BIT(2)|BIT(3) |
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#define EBI2_CS2_ENABLE_MASK BIT(4) |
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#define EBI2_CS3_ENABLE_MASK BIT(5) |
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#define EBI2_CS4_ENABLE_MASK BIT(6)|BIT(7) |
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#define EBI2_CS5_ENABLE_MASK BIT(8)|BIT(9) |
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#define EBI2_CSN_MASK GENMASK(9, 0) |
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#define EBI2_XMEM_CFG 0x0000 /* Power management etc */ |
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/* |
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* SLOW CSn CFG |
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* |
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* Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the |
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* memory continues to drive the data bus after OE is de-asserted. |
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* Inserted when reading one CS and switching to another CS or read |
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* followed by write on the same CS. Valid values 0 thru 15. |
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* Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after |
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* every write minimum 1. The data out is driven from the time WE is |
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* asserted until CS is asserted. With a hold of 1, the CS stays |
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* active for 1 extra cycle etc. Valid values 0 thru 15. |
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* Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first |
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* write to a page or burst memory |
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* Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first |
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* read to a page or burst memory |
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* Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle |
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* so 1 thru 16 cycles. |
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* Bits 3-0: RD_WAIT number of wait cycles for every read access, 0=1 cycle |
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* so 1 thru 16 cycles. |
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*/ |
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#define EBI2_XMEM_CS0_SLOW_CFG 0x0008 |
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#define EBI2_XMEM_CS1_SLOW_CFG 0x000C |
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#define EBI2_XMEM_CS2_SLOW_CFG 0x0010 |
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#define EBI2_XMEM_CS3_SLOW_CFG 0x0014 |
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#define EBI2_XMEM_CS4_SLOW_CFG 0x0018 |
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#define EBI2_XMEM_CS5_SLOW_CFG 0x001C |
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#define EBI2_XMEM_RECOVERY_SHIFT 28 |
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#define EBI2_XMEM_WR_HOLD_SHIFT 24 |
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#define EBI2_XMEM_WR_DELTA_SHIFT 16 |
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#define EBI2_XMEM_RD_DELTA_SHIFT 8 |
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#define EBI2_XMEM_WR_WAIT_SHIFT 4 |
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#define EBI2_XMEM_RD_WAIT_SHIFT 0 |
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/* |
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* FAST CSn CFG |
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* Bits 31-28: ? |
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* Bits 27-24: RD_HOLD: the length in cycles of the first segment of a read |
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* transfer. For a single read trandfer this will be the time |
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* from CS assertion to OE assertion. |
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* Bits 18-24: ? |
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* Bits 17-16: ADV_OE_RECOVERY, the number of cycles elapsed before an OE |
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* assertion, with respect to the cycle where ADV is asserted. |
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* 2 means 2 cycles between ADV and OE. Values 0, 1, 2 or 3. |
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* Bits 5: ADDR_HOLD_ENA, The address is held for an extra cycle to meet |
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* hold time requirements with ADV assertion. |
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* |
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* The manual mentions "write precharge cycles" and "precharge cycles". |
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* We have not been able to figure out which bit fields these correspond to |
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* in the hardware, or what valid values exist. The current hypothesis is that |
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* this is something just used on the FAST chip selects. There is also a "byte |
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* device enable" flag somewhere for 8bit memories. |
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*/ |
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#define EBI2_XMEM_CS0_FAST_CFG 0x0028 |
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#define EBI2_XMEM_CS1_FAST_CFG 0x002C |
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#define EBI2_XMEM_CS2_FAST_CFG 0x0030 |
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#define EBI2_XMEM_CS3_FAST_CFG 0x0034 |
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#define EBI2_XMEM_CS4_FAST_CFG 0x0038 |
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#define EBI2_XMEM_CS5_FAST_CFG 0x003C |
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#define EBI2_XMEM_RD_HOLD_SHIFT 24 |
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#define EBI2_XMEM_ADV_OE_RECOVERY_SHIFT 16 |
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#define EBI2_XMEM_ADDR_HOLD_ENA_SHIFT 5 |
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/** |
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* struct cs_data - struct with info on a chipselect setting |
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* @enable_mask: mask to enable the chipselect in the EBI2 config |
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* @slow_cfg0: offset to XMEMC slow CS config |
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* @fast_cfg1: offset to XMEMC fast CS config |
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*/ |
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struct cs_data { |
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u32 enable_mask; |
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u16 slow_cfg; |
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u16 fast_cfg; |
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}; |
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static const struct cs_data cs_info[] = { |
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{ |
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/* CS0 */ |
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.enable_mask = EBI2_CS0_ENABLE_MASK, |
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.slow_cfg = EBI2_XMEM_CS0_SLOW_CFG, |
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.fast_cfg = EBI2_XMEM_CS0_FAST_CFG, |
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}, |
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{ |
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/* CS1 */ |
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.enable_mask = EBI2_CS1_ENABLE_MASK, |
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.slow_cfg = EBI2_XMEM_CS1_SLOW_CFG, |
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.fast_cfg = EBI2_XMEM_CS1_FAST_CFG, |
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}, |
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{ |
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/* CS2 */ |
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.enable_mask = EBI2_CS2_ENABLE_MASK, |
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.slow_cfg = EBI2_XMEM_CS2_SLOW_CFG, |
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.fast_cfg = EBI2_XMEM_CS2_FAST_CFG, |
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}, |
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{ |
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/* CS3 */ |
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.enable_mask = EBI2_CS3_ENABLE_MASK, |
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.slow_cfg = EBI2_XMEM_CS3_SLOW_CFG, |
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.fast_cfg = EBI2_XMEM_CS3_FAST_CFG, |
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}, |
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{ |
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/* CS4 */ |
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.enable_mask = EBI2_CS4_ENABLE_MASK, |
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.slow_cfg = EBI2_XMEM_CS4_SLOW_CFG, |
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.fast_cfg = EBI2_XMEM_CS4_FAST_CFG, |
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}, |
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{ |
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/* CS5 */ |
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.enable_mask = EBI2_CS5_ENABLE_MASK, |
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.slow_cfg = EBI2_XMEM_CS5_SLOW_CFG, |
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.fast_cfg = EBI2_XMEM_CS5_FAST_CFG, |
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}, |
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}; |
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/** |
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* struct ebi2_xmem_prop - describes an XMEM config property |
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* @prop: the device tree binding name |
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* @max: maximum value for the property |
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* @slowreg: true if this property is in the SLOW CS config register |
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* else it is assumed to be in the FAST config register |
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* @shift: the bit field start in the SLOW or FAST register for this |
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* property |
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*/ |
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struct ebi2_xmem_prop { |
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const char *prop; |
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u32 max; |
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bool slowreg; |
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u16 shift; |
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}; |
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static const struct ebi2_xmem_prop xmem_props[] = { |
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{ |
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.prop = "qcom,xmem-recovery-cycles", |
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.max = 15, |
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.slowreg = true, |
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.shift = EBI2_XMEM_RECOVERY_SHIFT, |
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}, |
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{ |
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.prop = "qcom,xmem-write-hold-cycles", |
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.max = 15, |
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.slowreg = true, |
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.shift = EBI2_XMEM_WR_HOLD_SHIFT, |
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}, |
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{ |
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.prop = "qcom,xmem-write-delta-cycles", |
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.max = 255, |
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.slowreg = true, |
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.shift = EBI2_XMEM_WR_DELTA_SHIFT, |
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}, |
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{ |
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.prop = "qcom,xmem-read-delta-cycles", |
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.max = 255, |
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.slowreg = true, |
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.shift = EBI2_XMEM_RD_DELTA_SHIFT, |
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}, |
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{ |
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.prop = "qcom,xmem-write-wait-cycles", |
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.max = 15, |
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.slowreg = true, |
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.shift = EBI2_XMEM_WR_WAIT_SHIFT, |
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}, |
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{ |
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.prop = "qcom,xmem-read-wait-cycles", |
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.max = 15, |
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.slowreg = true, |
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.shift = EBI2_XMEM_RD_WAIT_SHIFT, |
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}, |
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{ |
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.prop = "qcom,xmem-address-hold-enable", |
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.max = 1, /* boolean prop */ |
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.slowreg = false, |
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.shift = EBI2_XMEM_ADDR_HOLD_ENA_SHIFT, |
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}, |
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{ |
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.prop = "qcom,xmem-adv-to-oe-recovery-cycles", |
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.max = 3, |
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.slowreg = false, |
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.shift = EBI2_XMEM_ADV_OE_RECOVERY_SHIFT, |
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}, |
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{ |
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.prop = "qcom,xmem-read-hold-cycles", |
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.max = 15, |
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.slowreg = false, |
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.shift = EBI2_XMEM_RD_HOLD_SHIFT, |
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}, |
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}; |
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static void qcom_ebi2_setup_chipselect(struct device_node *np, |
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struct device *dev, |
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void __iomem *ebi2_base, |
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void __iomem *ebi2_xmem, |
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u32 csindex) |
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{ |
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const struct cs_data *csd; |
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u32 slowcfg, fastcfg; |
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u32 val; |
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int ret; |
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int i; |
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csd = &cs_info[csindex]; |
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val = readl(ebi2_base); |
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val |= csd->enable_mask; |
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writel(val, ebi2_base); |
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dev_dbg(dev, "enabled CS%u\n", csindex); |
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/* Next set up the XMEMC */ |
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slowcfg = 0; |
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fastcfg = 0; |
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for (i = 0; i < ARRAY_SIZE(xmem_props); i++) { |
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const struct ebi2_xmem_prop *xp = &xmem_props[i]; |
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/* All are regular u32 values */ |
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ret = of_property_read_u32(np, xp->prop, &val); |
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if (ret) { |
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dev_dbg(dev, "could not read %s for CS%d\n", |
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xp->prop, csindex); |
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continue; |
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} |
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/* First check boolean props */ |
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if (xp->max == 1 && val) { |
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if (xp->slowreg) |
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slowcfg |= BIT(xp->shift); |
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else |
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fastcfg |= BIT(xp->shift); |
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dev_dbg(dev, "set %s flag\n", xp->prop); |
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continue; |
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} |
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/* We're dealing with an u32 */ |
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if (val > xp->max) { |
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dev_err(dev, |
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"too high value for %s: %u, capped at %u\n", |
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xp->prop, val, xp->max); |
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val = xp->max; |
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} |
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if (xp->slowreg) |
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slowcfg |= (val << xp->shift); |
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else |
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fastcfg |= (val << xp->shift); |
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dev_dbg(dev, "set %s to %u\n", xp->prop, val); |
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} |
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dev_info(dev, "CS%u: SLOW CFG 0x%08x, FAST CFG 0x%08x\n", |
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csindex, slowcfg, fastcfg); |
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if (slowcfg) |
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writel(slowcfg, ebi2_xmem + csd->slow_cfg); |
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if (fastcfg) |
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writel(fastcfg, ebi2_xmem + csd->fast_cfg); |
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} |
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static int qcom_ebi2_probe(struct platform_device *pdev) |
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{ |
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struct device_node *np = pdev->dev.of_node; |
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struct device_node *child; |
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struct device *dev = &pdev->dev; |
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struct resource *res; |
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void __iomem *ebi2_base; |
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void __iomem *ebi2_xmem; |
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struct clk *ebi2xclk; |
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struct clk *ebi2clk; |
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bool have_children = false; |
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u32 val; |
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int ret; |
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ebi2xclk = devm_clk_get(dev, "ebi2x"); |
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if (IS_ERR(ebi2xclk)) |
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return PTR_ERR(ebi2xclk); |
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ret = clk_prepare_enable(ebi2xclk); |
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if (ret) { |
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dev_err(dev, "could not enable EBI2X clk (%d)\n", ret); |
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return ret; |
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} |
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ebi2clk = devm_clk_get(dev, "ebi2"); |
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if (IS_ERR(ebi2clk)) { |
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ret = PTR_ERR(ebi2clk); |
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goto err_disable_2x_clk; |
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} |
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ret = clk_prepare_enable(ebi2clk); |
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if (ret) { |
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dev_err(dev, "could not enable EBI2 clk\n"); |
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goto err_disable_2x_clk; |
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} |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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ebi2_base = devm_ioremap_resource(dev, res); |
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if (IS_ERR(ebi2_base)) { |
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ret = PTR_ERR(ebi2_base); |
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goto err_disable_clk; |
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} |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
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ebi2_xmem = devm_ioremap_resource(dev, res); |
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if (IS_ERR(ebi2_xmem)) { |
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ret = PTR_ERR(ebi2_xmem); |
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goto err_disable_clk; |
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} |
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/* Allegedly this turns the power save mode off */ |
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writel(0UL, ebi2_xmem + EBI2_XMEM_CFG); |
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/* Disable all chipselects */ |
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val = readl(ebi2_base); |
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val &= ~EBI2_CSN_MASK; |
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writel(val, ebi2_base); |
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/* Walk over the child nodes and see what chipselects we use */ |
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for_each_available_child_of_node(np, child) { |
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u32 csindex; |
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/* Figure out the chipselect */ |
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ret = of_property_read_u32(child, "reg", &csindex); |
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if (ret) { |
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of_node_put(child); |
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return ret; |
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} |
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if (csindex > 5) { |
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dev_err(dev, |
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"invalid chipselect %u, we only support 0-5\n", |
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csindex); |
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continue; |
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} |
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qcom_ebi2_setup_chipselect(child, |
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dev, |
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ebi2_base, |
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ebi2_xmem, |
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csindex); |
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/* We have at least one child */ |
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have_children = true; |
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} |
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if (have_children) |
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return of_platform_default_populate(np, NULL, dev); |
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return 0; |
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err_disable_clk: |
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clk_disable_unprepare(ebi2clk); |
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err_disable_2x_clk: |
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clk_disable_unprepare(ebi2xclk); |
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return ret; |
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} |
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static const struct of_device_id qcom_ebi2_of_match[] = { |
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{ .compatible = "qcom,msm8660-ebi2", }, |
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{ .compatible = "qcom,apq8060-ebi2", }, |
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{ } |
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}; |
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static struct platform_driver qcom_ebi2_driver = { |
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.probe = qcom_ebi2_probe, |
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.driver = { |
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.name = "qcom-ebi2", |
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.of_match_table = qcom_ebi2_of_match, |
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}, |
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}; |
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module_platform_driver(qcom_ebi2_driver); |
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MODULE_AUTHOR("Linus Walleij <[email protected]>"); |
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MODULE_DESCRIPTION("Qualcomm EBI2 driver"); |
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MODULE_LICENSE("GPL");
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