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119 lines
4.0 KiB
119 lines
4.0 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright (C) 2008-2009 Michal Simek <[email protected]> |
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* Copyright (C) 2008-2009 PetaLogix |
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* Copyright (C) 2006 Atmark Techno, Inc. |
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*/ |
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#ifndef _ASM_MICROBLAZE_MMU_H |
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#define _ASM_MICROBLAZE_MMU_H |
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# ifdef __KERNEL__ |
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# ifndef __ASSEMBLY__ |
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/* Default "unsigned long" context */ |
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typedef unsigned long mm_context_t; |
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/* Hardware Page Table Entry */ |
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typedef struct _PTE { |
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unsigned long v:1; /* Entry is valid */ |
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unsigned long vsid:24; /* Virtual segment identifier */ |
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unsigned long h:1; /* Hash algorithm indicator */ |
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unsigned long api:6; /* Abbreviated page index */ |
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unsigned long rpn:20; /* Real (physical) page number */ |
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unsigned long :3; /* Unused */ |
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unsigned long r:1; /* Referenced */ |
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unsigned long c:1; /* Changed */ |
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unsigned long w:1; /* Write-thru cache mode */ |
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unsigned long i:1; /* Cache inhibited */ |
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unsigned long m:1; /* Memory coherence */ |
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unsigned long g:1; /* Guarded */ |
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unsigned long :1; /* Unused */ |
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unsigned long pp:2; /* Page protection */ |
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} PTE; |
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/* Values for PP (assumes Ks=0, Kp=1) */ |
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# define PP_RWXX 0 /* Supervisor read/write, User none */ |
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# define PP_RWRX 1 /* Supervisor read/write, User read */ |
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# define PP_RWRW 2 /* Supervisor read/write, User read/write */ |
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# define PP_RXRX 3 /* Supervisor read, User read */ |
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/* Segment Register */ |
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typedef struct _SEGREG { |
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unsigned long t:1; /* Normal or I/O type */ |
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unsigned long ks:1; /* Supervisor 'key' (normally 0) */ |
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unsigned long kp:1; /* User 'key' (normally 1) */ |
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unsigned long n:1; /* No-execute */ |
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unsigned long :4; /* Unused */ |
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unsigned long vsid:24; /* Virtual Segment Identifier */ |
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} SEGREG; |
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extern void _tlbie(unsigned long va); /* invalidate a TLB entry */ |
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extern void _tlbia(void); /* invalidate all TLB entries */ |
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/* |
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* tlb_skip size stores actual number skipped TLBs from TLB0 - every directy TLB |
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* mapping has to increase tlb_skip size. |
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*/ |
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extern u32 tlb_skip; |
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# endif /* __ASSEMBLY__ */ |
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/* |
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* The MicroBlaze processor has a TLB architecture identical to PPC-40x. The |
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* instruction and data sides share a unified, 64-entry, semi-associative |
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* TLB which is maintained totally under software control. In addition, the |
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* instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative |
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* TLB which serves as a first level to the shared TLB. These two TLBs are |
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* known as the UTLB and ITLB, respectively. |
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*/ |
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# define MICROBLAZE_TLB_SIZE 64 |
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/* For cases when you want to skip some TLB entries */ |
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# define MICROBLAZE_TLB_SKIP 0 |
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/* Use the last TLB for temporary access to LMB */ |
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# define MICROBLAZE_LMB_TLB_ID 63 |
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/* |
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* TLB entries are defined by a "high" tag portion and a "low" data |
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* portion. The data portion is 32-bits. |
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* |
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* TLB entries are managed entirely under software control by reading, |
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* writing, and searching using the MTS and MFS instructions. |
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*/ |
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# define TLB_LO 1 |
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# define TLB_HI 0 |
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# define TLB_DATA TLB_LO |
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# define TLB_TAG TLB_HI |
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/* Tag portion */ |
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# define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ |
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# define TLB_PAGESZ_MASK 0x00000380 |
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# define TLB_PAGESZ(x) (((x) & 0x7) << 7) |
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# define PAGESZ_1K 0 |
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# define PAGESZ_4K 1 |
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# define PAGESZ_16K 2 |
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# define PAGESZ_64K 3 |
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# define PAGESZ_256K 4 |
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# define PAGESZ_1M 5 |
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# define PAGESZ_4M 6 |
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# define PAGESZ_16M 7 |
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# define TLB_VALID 0x00000040 /* Entry is valid */ |
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/* Data portion */ |
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# define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ |
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# define TLB_PERM_MASK 0x00000300 |
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# define TLB_EX 0x00000200 /* Instruction execution allowed */ |
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# define TLB_WR 0x00000100 /* Writes permitted */ |
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# define TLB_ZSEL_MASK 0x000000F0 |
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# define TLB_ZSEL(x) (((x) & 0xF) << 4) |
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# define TLB_ATTR_MASK 0x0000000F |
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# define TLB_W 0x00000008 /* Caching is write-through */ |
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# define TLB_I 0x00000004 /* Caching is inhibited */ |
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# define TLB_M 0x00000002 /* Memory is coherent */ |
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# define TLB_G 0x00000001 /* Memory is guarded from prefetch */ |
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# endif /* __KERNEL__ */ |
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#endif /* _ASM_MICROBLAZE_MMU_H */
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