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198 lines
8.6 KiB
198 lines
8.6 KiB
============================= |
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MMUv3 initialization sequence |
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============================= |
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The code in the initialize_mmu macro sets up MMUv3 memory mapping |
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identically to MMUv2 fixed memory mapping. Depending on |
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CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX symbol this code is |
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located in addresses it was linked for (symbol undefined), or not |
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(symbol defined), so it needs to be position-independent. |
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The code has the following assumptions: |
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- This code fragment is run only on an MMU v3. |
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- TLBs are in their reset state. |
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- ITLBCFG and DTLBCFG are zero (reset state). |
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- RASID is 0x04030201 (reset state). |
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- PS.RING is zero (reset state). |
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- LITBASE is zero (reset state, PC-relative literals); required to be PIC. |
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TLB setup proceeds along the following steps. |
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Legend: |
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- VA = virtual address (two upper nibbles of it); |
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- PA = physical address (two upper nibbles of it); |
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- pc = physical range that contains this code; |
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After step 2, we jump to virtual address in the range 0x40000000..0x5fffffff |
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or 0x00000000..0x1fffffff, depending on whether the kernel was loaded below |
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0x40000000 or above. That address corresponds to next instruction to execute |
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in this code. After step 4, we jump to intended (linked) address of this code. |
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The scheme below assumes that the kernel is loaded below 0x40000000. |
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====== ===== ===== ===== ===== ====== ===== ===== |
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- Step0 Step1 Step2 Step3 Step4 Step5 |
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VA PA PA PA PA VA PA PA |
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====== ===== ===== ===== ===== ====== ===== ===== |
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E0..FF -> E0 -> E0 -> E0 F0..FF -> F0 -> F0 |
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C0..DF -> C0 -> C0 -> C0 E0..EF -> F0 -> F0 |
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A0..BF -> A0 -> A0 -> A0 D8..DF -> 00 -> 00 |
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80..9F -> 80 -> 80 -> 80 D0..D7 -> 00 -> 00 |
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60..7F -> 60 -> 60 -> 60 |
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40..5F -> 40 -> pc -> pc 40..5F -> pc |
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20..3F -> 20 -> 20 -> 20 |
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00..1F -> 00 -> 00 -> 00 |
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====== ===== ===== ===== ===== ====== ===== ===== |
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The default location of IO peripherals is above 0xf0000000. This may be changed |
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using a "ranges" property in a device tree simple-bus node. See the Devicetree |
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Specification, section 4.5 for details on the syntax and semantics of |
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simple-bus nodes. The following limitations apply: |
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1. Only top level simple-bus nodes are considered |
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2. Only one (first) simple-bus node is considered |
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3. Empty "ranges" properties are not supported |
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4. Only the first triplet in the "ranges" property is considered |
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5. The parent-bus-address value is rounded down to the nearest 256MB boundary |
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6. The IO area covers the entire 256MB segment of parent-bus-address; the |
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"ranges" triplet length field is ignored |
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MMUv3 address space layouts. |
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============================ |
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Default MMUv2-compatible layout:: |
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Symbol VADDR Size |
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+------------------+ |
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| Userspace | 0x00000000 TASK_SIZE |
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+------------------+ 0x40000000 |
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+------------------+ |
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| Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE |
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+------------------+ |
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| KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE |
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+------------------+ 0x8e400000 |
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+------------------+ |
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| VMALLOC area | VMALLOC_START 0xc0000000 128MB - 64KB |
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+------------------+ VMALLOC_END |
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+------------------+ |
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| Cache aliasing | TLBTEMP_BASE_1 0xc8000000 DCACHE_WAY_SIZE |
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| remap area 1 | |
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+------------------+ |
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| Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE |
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| remap area 2 | |
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+------------------+ |
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+------------------+ |
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| KMAP area | PKMAP_BASE PTRS_PER_PTE * |
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| | DCACHE_N_COLORS * |
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| | PAGE_SIZE |
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| | (4MB * DCACHE_N_COLORS) |
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+------------------+ |
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| Atomic KMAP area | FIXADDR_START KM_TYPE_NR * |
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| | NR_CPUS * |
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| | DCACHE_N_COLORS * |
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| | PAGE_SIZE |
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+------------------+ FIXADDR_TOP 0xcffff000 |
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+------------------+ |
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| Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xd0000000 128MB |
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+------------------+ |
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| Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xd8000000 128MB |
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+------------------+ |
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| Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB |
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+------------------+ |
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| Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB |
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+------------------+ |
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256MB cached + 256MB uncached layout:: |
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Symbol VADDR Size |
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+------------------+ |
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| Userspace | 0x00000000 TASK_SIZE |
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+------------------+ 0x40000000 |
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+------------------+ |
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| Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE |
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+------------------+ |
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| KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE |
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+------------------+ 0x8e400000 |
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+------------------+ |
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| VMALLOC area | VMALLOC_START 0xa0000000 128MB - 64KB |
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+------------------+ VMALLOC_END |
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+------------------+ |
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| Cache aliasing | TLBTEMP_BASE_1 0xa8000000 DCACHE_WAY_SIZE |
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| remap area 1 | |
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+------------------+ |
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| Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE |
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| remap area 2 | |
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+------------------+ |
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+------------------+ |
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| KMAP area | PKMAP_BASE PTRS_PER_PTE * |
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| | DCACHE_N_COLORS * |
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| | PAGE_SIZE |
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| | (4MB * DCACHE_N_COLORS) |
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+------------------+ |
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| Atomic KMAP area | FIXADDR_START KM_TYPE_NR * |
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| | NR_CPUS * |
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| | DCACHE_N_COLORS * |
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| | PAGE_SIZE |
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+------------------+ FIXADDR_TOP 0xaffff000 |
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+------------------+ |
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| Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xb0000000 256MB |
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+------------------+ |
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| Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 256MB |
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+------------------+ |
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+------------------+ |
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| Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB |
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+------------------+ |
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| Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB |
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+------------------+ |
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512MB cached + 512MB uncached layout:: |
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Symbol VADDR Size |
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+------------------+ |
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| Userspace | 0x00000000 TASK_SIZE |
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+------------------+ 0x40000000 |
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+------------------+ |
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| Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE |
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+------------------+ |
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| KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE |
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+------------------+ 0x8e400000 |
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+------------------+ |
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| VMALLOC area | VMALLOC_START 0x90000000 128MB - 64KB |
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+------------------+ VMALLOC_END |
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+------------------+ |
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| Cache aliasing | TLBTEMP_BASE_1 0x98000000 DCACHE_WAY_SIZE |
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| remap area 1 | |
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+------------------+ |
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| Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE |
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| remap area 2 | |
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+------------------+ |
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+------------------+ |
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| KMAP area | PKMAP_BASE PTRS_PER_PTE * |
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| | DCACHE_N_COLORS * |
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| | PAGE_SIZE |
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| | (4MB * DCACHE_N_COLORS) |
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+------------------+ |
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| Atomic KMAP area | FIXADDR_START KM_TYPE_NR * |
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| | NR_CPUS * |
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| | DCACHE_N_COLORS * |
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| | PAGE_SIZE |
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+------------------+ FIXADDR_TOP 0x9ffff000 |
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+------------------+ |
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| Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xa0000000 512MB |
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+------------------+ |
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| Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 512MB |
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+------------------+ |
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| Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB |
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+------------------+ |
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| Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB |
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+------------------+
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