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51 lines
2.2 KiB
51 lines
2.2 KiB
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Atomic Operation Control (ATOMCTL) Register |
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We Have Atomic Operation Control (ATOMCTL) Register. |
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This register determines the effect of using a S32C1I instruction |
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with various combinations of: |
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1. With and without an Coherent Cache Controller which |
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can do Atomic Transactions to the memory internally. |
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2. With and without An Intelligent Memory Controller which |
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can do Atomic Transactions itself. |
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The Core comes up with a default value of for the three types of cache ops:: |
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0x28: (WB: Internal, WT: Internal, BY:Exception) |
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On the FPGA Cards we typically simulate an Intelligent Memory controller |
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which can implement RCW transactions. For FPGA cards with an External |
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Memory controller we let it to the atomic operations internally while |
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doing a Cached (WB) transaction and use the Memory RCW for un-cached |
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operations. |
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For systems without an coherent cache controller, non-MX, we always |
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use the memory controllers RCW, thought non-MX controlers likely |
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support the Internal Operation. |
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CUSTOMER-WARNING: |
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Virtually all customers buy their memory controllers from vendors that |
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don't support atomic RCW memory transactions and will likely want to |
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configure this register to not use RCW. |
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Developers might find using RCW in Bypass mode convenient when testing |
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with the cache being bypassed; for example studying cache alias problems. |
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See Section 4.3.12.4 of ISA; Bits:: |
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WB WT BY |
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5 4 | 3 2 | 1 0 |
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========= ================== ================== =============== |
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2 Bit |
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Field |
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Values WB - Write Back WT - Write Thru BY - Bypass |
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========= ================== ================== =============== |
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0 Exception Exception Exception |
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1 RCW Transaction RCW Transaction RCW Transaction |
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2 Internal Operation Internal Operation Reserved |
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3 Reserved Reserved Reserved |
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========= ================== ================== ===============
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