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367 lines
9.9 KiB
367 lines
9.9 KiB
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On atomic types (atomic_t atomic64_t and atomic_long_t). |
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The atomic type provides an interface to the architecture's means of atomic |
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RMW operations between CPUs (atomic operations on MMIO are not supported and |
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can lead to fatal traps on some platforms). |
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API |
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--- |
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The 'full' API consists of (atomic64_ and atomic_long_ prefixes omitted for |
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brevity): |
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Non-RMW ops: |
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atomic_read(), atomic_set() |
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atomic_read_acquire(), atomic_set_release() |
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RMW atomic operations: |
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Arithmetic: |
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atomic_{add,sub,inc,dec}() |
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atomic_{add,sub,inc,dec}_return{,_relaxed,_acquire,_release}() |
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atomic_fetch_{add,sub,inc,dec}{,_relaxed,_acquire,_release}() |
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Bitwise: |
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atomic_{and,or,xor,andnot}() |
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atomic_fetch_{and,or,xor,andnot}{,_relaxed,_acquire,_release}() |
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Swap: |
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atomic_xchg{,_relaxed,_acquire,_release}() |
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atomic_cmpxchg{,_relaxed,_acquire,_release}() |
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atomic_try_cmpxchg{,_relaxed,_acquire,_release}() |
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Reference count (but please see refcount_t): |
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atomic_add_unless(), atomic_inc_not_zero() |
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atomic_sub_and_test(), atomic_dec_and_test() |
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Misc: |
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atomic_inc_and_test(), atomic_add_negative() |
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atomic_dec_unless_positive(), atomic_inc_unless_negative() |
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Barriers: |
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smp_mb__{before,after}_atomic() |
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TYPES (signed vs unsigned) |
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----- |
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While atomic_t, atomic_long_t and atomic64_t use int, long and s64 |
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respectively (for hysterical raisins), the kernel uses -fno-strict-overflow |
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(which implies -fwrapv) and defines signed overflow to behave like |
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2s-complement. |
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Therefore, an explicitly unsigned variant of the atomic ops is strictly |
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unnecessary and we can simply cast, there is no UB. |
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There was a bug in UBSAN prior to GCC-8 that would generate UB warnings for |
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signed types. |
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With this we also conform to the C/C++ _Atomic behaviour and things like |
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P1236R1. |
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SEMANTICS |
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--------- |
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Non-RMW ops: |
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The non-RMW ops are (typically) regular LOADs and STOREs and are canonically |
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implemented using READ_ONCE(), WRITE_ONCE(), smp_load_acquire() and |
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smp_store_release() respectively. Therefore, if you find yourself only using |
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the Non-RMW operations of atomic_t, you do not in fact need atomic_t at all |
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and are doing it wrong. |
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A note for the implementation of atomic_set{}() is that it must not break the |
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atomicity of the RMW ops. That is: |
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C Atomic-RMW-ops-are-atomic-WRT-atomic_set |
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{ |
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atomic_t v = ATOMIC_INIT(1); |
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} |
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P0(atomic_t *v) |
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{ |
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(void)atomic_add_unless(v, 1, 0); |
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} |
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P1(atomic_t *v) |
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{ |
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atomic_set(v, 0); |
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} |
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exists |
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(v=2) |
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In this case we would expect the atomic_set() from CPU1 to either happen |
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before the atomic_add_unless(), in which case that latter one would no-op, or |
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_after_ in which case we'd overwrite its result. In no case is "2" a valid |
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outcome. |
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This is typically true on 'normal' platforms, where a regular competing STORE |
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will invalidate a LL/SC or fail a CMPXCHG. |
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The obvious case where this is not so is when we need to implement atomic ops |
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with a lock: |
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CPU0 CPU1 |
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atomic_add_unless(v, 1, 0); |
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lock(); |
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ret = READ_ONCE(v->counter); // == 1 |
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atomic_set(v, 0); |
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if (ret != u) WRITE_ONCE(v->counter, 0); |
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WRITE_ONCE(v->counter, ret + 1); |
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unlock(); |
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the typical solution is to then implement atomic_set{}() with atomic_xchg(). |
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RMW ops: |
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These come in various forms: |
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- plain operations without return value: atomic_{}() |
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- operations which return the modified value: atomic_{}_return() |
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these are limited to the arithmetic operations because those are |
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reversible. Bitops are irreversible and therefore the modified value |
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is of dubious utility. |
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- operations which return the original value: atomic_fetch_{}() |
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- swap operations: xchg(), cmpxchg() and try_cmpxchg() |
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- misc; the special purpose operations that are commonly used and would, |
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given the interface, normally be implemented using (try_)cmpxchg loops but |
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are time critical and can, (typically) on LL/SC architectures, be more |
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efficiently implemented. |
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All these operations are SMP atomic; that is, the operations (for a single |
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atomic variable) can be fully ordered and no intermediate state is lost or |
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visible. |
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ORDERING (go read memory-barriers.txt first) |
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-------- |
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The rule of thumb: |
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- non-RMW operations are unordered; |
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- RMW operations that have no return value are unordered; |
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- RMW operations that have a return value are fully ordered; |
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- RMW operations that are conditional are unordered on FAILURE, |
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otherwise the above rules apply. |
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Except of course when an operation has an explicit ordering like: |
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{}_relaxed: unordered |
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{}_acquire: the R of the RMW (or atomic_read) is an ACQUIRE |
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{}_release: the W of the RMW (or atomic_set) is a RELEASE |
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Where 'unordered' is against other memory locations. Address dependencies are |
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not defeated. |
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Fully ordered primitives are ordered against everything prior and everything |
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subsequent. Therefore a fully ordered primitive is like having an smp_mb() |
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before and an smp_mb() after the primitive. |
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The barriers: |
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smp_mb__{before,after}_atomic() |
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only apply to the RMW atomic ops and can be used to augment/upgrade the |
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ordering inherent to the op. These barriers act almost like a full smp_mb(): |
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smp_mb__before_atomic() orders all earlier accesses against the RMW op |
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itself and all accesses following it, and smp_mb__after_atomic() orders all |
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later accesses against the RMW op and all accesses preceding it. However, |
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accesses between the smp_mb__{before,after}_atomic() and the RMW op are not |
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ordered, so it is advisable to place the barrier right next to the RMW atomic |
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op whenever possible. |
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These helper barriers exist because architectures have varying implicit |
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ordering on their SMP atomic primitives. For example our TSO architectures |
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provide full ordered atomics and these barriers are no-ops. |
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NOTE: when the atomic RmW ops are fully ordered, they should also imply a |
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compiler barrier. |
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Thus: |
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atomic_fetch_add(); |
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is equivalent to: |
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smp_mb__before_atomic(); |
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atomic_fetch_add_relaxed(); |
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smp_mb__after_atomic(); |
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However the atomic_fetch_add() might be implemented more efficiently. |
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Further, while something like: |
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smp_mb__before_atomic(); |
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atomic_dec(&X); |
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is a 'typical' RELEASE pattern, the barrier is strictly stronger than |
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a RELEASE because it orders preceding instructions against both the read |
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and write parts of the atomic_dec(), and against all following instructions |
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as well. Similarly, something like: |
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atomic_inc(&X); |
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smp_mb__after_atomic(); |
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is an ACQUIRE pattern (though very much not typical), but again the barrier is |
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strictly stronger than ACQUIRE. As illustrated: |
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C Atomic-RMW+mb__after_atomic-is-stronger-than-acquire |
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{ |
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} |
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P0(int *x, atomic_t *y) |
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{ |
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r0 = READ_ONCE(*x); |
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smp_rmb(); |
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r1 = atomic_read(y); |
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} |
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P1(int *x, atomic_t *y) |
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{ |
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atomic_inc(y); |
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smp_mb__after_atomic(); |
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WRITE_ONCE(*x, 1); |
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} |
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exists |
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(0:r0=1 /\ 0:r1=0) |
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This should not happen; but a hypothetical atomic_inc_acquire() -- |
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(void)atomic_fetch_inc_acquire() for instance -- would allow the outcome, |
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because it would not order the W part of the RMW against the following |
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WRITE_ONCE. Thus: |
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P0 P1 |
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t = LL.acq *y (0) |
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t++; |
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*x = 1; |
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r0 = *x (1) |
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RMB |
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r1 = *y (0) |
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SC *y, t; |
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is allowed. |
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CMPXCHG vs TRY_CMPXCHG |
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---------------------- |
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int atomic_cmpxchg(atomic_t *ptr, int old, int new); |
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bool atomic_try_cmpxchg(atomic_t *ptr, int *oldp, int new); |
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Both provide the same functionality, but try_cmpxchg() can lead to more |
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compact code. The functions relate like: |
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bool atomic_try_cmpxchg(atomic_t *ptr, int *oldp, int new) |
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{ |
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int ret, old = *oldp; |
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ret = atomic_cmpxchg(ptr, old, new); |
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if (ret != old) |
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*oldp = ret; |
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return ret == old; |
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} |
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and: |
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int atomic_cmpxchg(atomic_t *ptr, int old, int new) |
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{ |
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(void)atomic_try_cmpxchg(ptr, &old, new); |
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return old; |
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} |
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Usage: |
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old = atomic_read(&v); old = atomic_read(&v); |
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for (;;) { do { |
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new = func(old); new = func(old); |
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tmp = atomic_cmpxchg(&v, old, new); } while (!atomic_try_cmpxchg(&v, &old, new)); |
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if (tmp == old) |
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break; |
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old = tmp; |
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} |
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NB. try_cmpxchg() also generates better code on some platforms (notably x86) |
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where the function more closely matches the hardware instruction. |
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FORWARD PROGRESS |
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---------------- |
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In general strong forward progress is expected of all unconditional atomic |
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operations -- those in the Arithmetic and Bitwise classes and xchg(). However |
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a fair amount of code also requires forward progress from the conditional |
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atomic operations. |
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Specifically 'simple' cmpxchg() loops are expected to not starve one another |
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indefinitely. However, this is not evident on LL/SC architectures, because |
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while an LL/SC architecure 'can/should/must' provide forward progress |
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guarantees between competing LL/SC sections, such a guarantee does not |
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transfer to cmpxchg() implemented using LL/SC. Consider: |
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old = atomic_read(&v); |
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do { |
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new = func(old); |
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} while (!atomic_try_cmpxchg(&v, &old, new)); |
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which on LL/SC becomes something like: |
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old = atomic_read(&v); |
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do { |
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new = func(old); |
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} while (!({ |
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volatile asm ("1: LL %[oldval], %[v]\n" |
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" CMP %[oldval], %[old]\n" |
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" BNE 2f\n" |
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" SC %[new], %[v]\n" |
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" BNE 1b\n" |
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"2:\n" |
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: [oldval] "=&r" (oldval), [v] "m" (v) |
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: [old] "r" (old), [new] "r" (new) |
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: "memory"); |
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success = (oldval == old); |
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if (!success) |
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old = oldval; |
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success; })); |
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However, even the forward branch from the failed compare can cause the LL/SC |
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to fail on some architectures, let alone whatever the compiler makes of the C |
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loop body. As a result there is no guarantee what so ever the cacheline |
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containing @v will stay on the local CPU and progress is made. |
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Even native CAS architectures can fail to provide forward progress for their |
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primitive (See Sparc64 for an example). |
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Such implementations are strongly encouraged to add exponential backoff loops |
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to a failed CAS in order to ensure some progress. Affected architectures are |
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also strongly encouraged to inspect/audit the atomic fallbacks, refcount_t and |
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their locking primitives.
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