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449 lines
11 KiB
449 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* tegra20_i2s.c - Tegra20 I2S driver |
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* |
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* Author: Stephen Warren <[email protected]> |
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* Copyright (C) 2010,2012 - NVIDIA, Inc. |
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* |
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* Based on code copyright/by: |
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* |
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* Copyright (c) 2009-2010, NVIDIA Corporation. |
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* Scott Peterson <[email protected]> |
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* |
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* Copyright (C) 2010 Google, Inc. |
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* Iliyan Malchev <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/device.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/regmap.h> |
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#include <linux/slab.h> |
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#include <sound/core.h> |
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#include <sound/pcm.h> |
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#include <sound/pcm_params.h> |
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#include <sound/soc.h> |
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#include <sound/dmaengine_pcm.h> |
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#include "tegra20_i2s.h" |
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#define DRV_NAME "tegra20-i2s" |
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static int tegra20_i2s_runtime_suspend(struct device *dev) |
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{ |
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struct tegra20_i2s *i2s = dev_get_drvdata(dev); |
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clk_disable_unprepare(i2s->clk_i2s); |
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return 0; |
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} |
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static int tegra20_i2s_runtime_resume(struct device *dev) |
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{ |
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struct tegra20_i2s *i2s = dev_get_drvdata(dev); |
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int ret; |
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ret = clk_prepare_enable(i2s->clk_i2s); |
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if (ret) { |
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dev_err(dev, "clk_enable failed: %d\n", ret); |
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return ret; |
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} |
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return 0; |
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} |
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static int tegra20_i2s_set_fmt(struct snd_soc_dai *dai, |
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unsigned int fmt) |
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{ |
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struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
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unsigned int mask = 0, val = 0; |
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
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case SND_SOC_DAIFMT_NB_NF: |
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break; |
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default: |
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return -EINVAL; |
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} |
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mask |= TEGRA20_I2S_CTRL_MASTER_ENABLE; |
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
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case SND_SOC_DAIFMT_CBS_CFS: |
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val |= TEGRA20_I2S_CTRL_MASTER_ENABLE; |
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break; |
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case SND_SOC_DAIFMT_CBM_CFM: |
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break; |
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default: |
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return -EINVAL; |
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} |
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mask |= TEGRA20_I2S_CTRL_BIT_FORMAT_MASK | |
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TEGRA20_I2S_CTRL_LRCK_MASK; |
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
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case SND_SOC_DAIFMT_DSP_A: |
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val |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP; |
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val |= TEGRA20_I2S_CTRL_LRCK_L_LOW; |
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break; |
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case SND_SOC_DAIFMT_DSP_B: |
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val |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP; |
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val |= TEGRA20_I2S_CTRL_LRCK_R_LOW; |
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break; |
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case SND_SOC_DAIFMT_I2S: |
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val |= TEGRA20_I2S_CTRL_BIT_FORMAT_I2S; |
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val |= TEGRA20_I2S_CTRL_LRCK_L_LOW; |
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break; |
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case SND_SOC_DAIFMT_RIGHT_J: |
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val |= TEGRA20_I2S_CTRL_BIT_FORMAT_RJM; |
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val |= TEGRA20_I2S_CTRL_LRCK_L_LOW; |
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break; |
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case SND_SOC_DAIFMT_LEFT_J: |
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val |= TEGRA20_I2S_CTRL_BIT_FORMAT_LJM; |
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val |= TEGRA20_I2S_CTRL_LRCK_L_LOW; |
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break; |
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default: |
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return -EINVAL; |
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} |
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regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val); |
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return 0; |
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} |
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static int tegra20_i2s_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *dai) |
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{ |
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struct device *dev = dai->dev; |
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struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
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unsigned int mask, val; |
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int ret, sample_size, srate, i2sclock, bitcnt; |
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mask = TEGRA20_I2S_CTRL_BIT_SIZE_MASK; |
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switch (params_format(params)) { |
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case SNDRV_PCM_FORMAT_S16_LE: |
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val = TEGRA20_I2S_CTRL_BIT_SIZE_16; |
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sample_size = 16; |
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break; |
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case SNDRV_PCM_FORMAT_S24_LE: |
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val = TEGRA20_I2S_CTRL_BIT_SIZE_24; |
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sample_size = 24; |
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break; |
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case SNDRV_PCM_FORMAT_S32_LE: |
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val = TEGRA20_I2S_CTRL_BIT_SIZE_32; |
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sample_size = 32; |
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break; |
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default: |
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return -EINVAL; |
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} |
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mask |= TEGRA20_I2S_CTRL_FIFO_FORMAT_MASK; |
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val |= TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED; |
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regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val); |
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srate = params_rate(params); |
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/* Final "* 2" required by Tegra hardware */ |
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i2sclock = srate * params_channels(params) * sample_size * 2; |
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ret = clk_set_rate(i2s->clk_i2s, i2sclock); |
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if (ret) { |
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dev_err(dev, "Can't set I2S clock rate: %d\n", ret); |
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return ret; |
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} |
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bitcnt = (i2sclock / (2 * srate)) - 1; |
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if (bitcnt < 0 || bitcnt > TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US) |
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return -EINVAL; |
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val = bitcnt << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT; |
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if (i2sclock % (2 * srate)) |
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val |= TEGRA20_I2S_TIMING_NON_SYM_ENABLE; |
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regmap_write(i2s->regmap, TEGRA20_I2S_TIMING, val); |
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regmap_write(i2s->regmap, TEGRA20_I2S_FIFO_SCR, |
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TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS | |
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TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS); |
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return 0; |
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} |
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static void tegra20_i2s_start_playback(struct tegra20_i2s *i2s) |
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{ |
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regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, |
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TEGRA20_I2S_CTRL_FIFO1_ENABLE, |
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TEGRA20_I2S_CTRL_FIFO1_ENABLE); |
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} |
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static void tegra20_i2s_stop_playback(struct tegra20_i2s *i2s) |
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{ |
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regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, |
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TEGRA20_I2S_CTRL_FIFO1_ENABLE, 0); |
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} |
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static void tegra20_i2s_start_capture(struct tegra20_i2s *i2s) |
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{ |
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regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, |
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TEGRA20_I2S_CTRL_FIFO2_ENABLE, |
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TEGRA20_I2S_CTRL_FIFO2_ENABLE); |
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} |
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static void tegra20_i2s_stop_capture(struct tegra20_i2s *i2s) |
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{ |
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regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, |
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TEGRA20_I2S_CTRL_FIFO2_ENABLE, 0); |
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} |
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static int tegra20_i2s_trigger(struct snd_pcm_substream *substream, int cmd, |
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struct snd_soc_dai *dai) |
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{ |
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struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
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switch (cmd) { |
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case SNDRV_PCM_TRIGGER_START: |
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
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case SNDRV_PCM_TRIGGER_RESUME: |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
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tegra20_i2s_start_playback(i2s); |
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else |
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tegra20_i2s_start_capture(i2s); |
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break; |
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case SNDRV_PCM_TRIGGER_STOP: |
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
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case SNDRV_PCM_TRIGGER_SUSPEND: |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
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tegra20_i2s_stop_playback(i2s); |
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else |
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tegra20_i2s_stop_capture(i2s); |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int tegra20_i2s_probe(struct snd_soc_dai *dai) |
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{ |
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struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
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dai->capture_dma_data = &i2s->capture_dma_data; |
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dai->playback_dma_data = &i2s->playback_dma_data; |
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return 0; |
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} |
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static const struct snd_soc_dai_ops tegra20_i2s_dai_ops = { |
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.set_fmt = tegra20_i2s_set_fmt, |
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.hw_params = tegra20_i2s_hw_params, |
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.trigger = tegra20_i2s_trigger, |
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}; |
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static const struct snd_soc_dai_driver tegra20_i2s_dai_template = { |
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.probe = tegra20_i2s_probe, |
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.playback = { |
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.stream_name = "Playback", |
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.channels_min = 2, |
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.channels_max = 2, |
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.rates = SNDRV_PCM_RATE_8000_96000, |
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.formats = SNDRV_PCM_FMTBIT_S16_LE, |
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}, |
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.capture = { |
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.stream_name = "Capture", |
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.channels_min = 2, |
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.channels_max = 2, |
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.rates = SNDRV_PCM_RATE_8000_96000, |
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.formats = SNDRV_PCM_FMTBIT_S16_LE, |
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}, |
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.ops = &tegra20_i2s_dai_ops, |
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.symmetric_rate = 1, |
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}; |
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static const struct snd_soc_component_driver tegra20_i2s_component = { |
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.name = DRV_NAME, |
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}; |
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static bool tegra20_i2s_wr_rd_reg(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case TEGRA20_I2S_CTRL: |
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case TEGRA20_I2S_STATUS: |
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case TEGRA20_I2S_TIMING: |
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case TEGRA20_I2S_FIFO_SCR: |
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case TEGRA20_I2S_PCM_CTRL: |
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case TEGRA20_I2S_NW_CTRL: |
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case TEGRA20_I2S_TDM_CTRL: |
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case TEGRA20_I2S_TDM_TX_RX_CTRL: |
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case TEGRA20_I2S_FIFO1: |
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case TEGRA20_I2S_FIFO2: |
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return true; |
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default: |
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return false; |
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} |
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} |
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static bool tegra20_i2s_volatile_reg(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case TEGRA20_I2S_STATUS: |
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case TEGRA20_I2S_FIFO_SCR: |
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case TEGRA20_I2S_FIFO1: |
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case TEGRA20_I2S_FIFO2: |
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return true; |
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default: |
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return false; |
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} |
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} |
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static bool tegra20_i2s_precious_reg(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case TEGRA20_I2S_FIFO1: |
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case TEGRA20_I2S_FIFO2: |
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return true; |
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default: |
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return false; |
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} |
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} |
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static const struct regmap_config tegra20_i2s_regmap_config = { |
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.reg_bits = 32, |
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.reg_stride = 4, |
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.val_bits = 32, |
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.max_register = TEGRA20_I2S_FIFO2, |
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.writeable_reg = tegra20_i2s_wr_rd_reg, |
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.readable_reg = tegra20_i2s_wr_rd_reg, |
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.volatile_reg = tegra20_i2s_volatile_reg, |
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.precious_reg = tegra20_i2s_precious_reg, |
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.cache_type = REGCACHE_FLAT, |
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}; |
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static int tegra20_i2s_platform_probe(struct platform_device *pdev) |
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{ |
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struct tegra20_i2s *i2s; |
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struct resource *mem; |
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void __iomem *regs; |
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int ret; |
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i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_i2s), GFP_KERNEL); |
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if (!i2s) { |
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ret = -ENOMEM; |
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goto err; |
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} |
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dev_set_drvdata(&pdev->dev, i2s); |
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i2s->dai = tegra20_i2s_dai_template; |
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i2s->dai.name = dev_name(&pdev->dev); |
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i2s->clk_i2s = clk_get(&pdev->dev, NULL); |
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if (IS_ERR(i2s->clk_i2s)) { |
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dev_err(&pdev->dev, "Can't retrieve i2s clock\n"); |
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ret = PTR_ERR(i2s->clk_i2s); |
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goto err; |
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} |
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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regs = devm_ioremap_resource(&pdev->dev, mem); |
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if (IS_ERR(regs)) { |
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ret = PTR_ERR(regs); |
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goto err_clk_put; |
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} |
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i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, |
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&tegra20_i2s_regmap_config); |
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if (IS_ERR(i2s->regmap)) { |
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dev_err(&pdev->dev, "regmap init failed\n"); |
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ret = PTR_ERR(i2s->regmap); |
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goto err_clk_put; |
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} |
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i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2; |
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i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
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i2s->capture_dma_data.maxburst = 4; |
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i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1; |
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i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
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i2s->playback_dma_data.maxburst = 4; |
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pm_runtime_enable(&pdev->dev); |
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if (!pm_runtime_enabled(&pdev->dev)) { |
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ret = tegra20_i2s_runtime_resume(&pdev->dev); |
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if (ret) |
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goto err_pm_disable; |
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} |
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ret = snd_soc_register_component(&pdev->dev, &tegra20_i2s_component, |
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&i2s->dai, 1); |
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if (ret) { |
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dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); |
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ret = -ENOMEM; |
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goto err_suspend; |
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} |
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ret = tegra_pcm_platform_register(&pdev->dev); |
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if (ret) { |
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dev_err(&pdev->dev, "Could not register PCM: %d\n", ret); |
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goto err_unregister_component; |
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} |
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return 0; |
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err_unregister_component: |
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snd_soc_unregister_component(&pdev->dev); |
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err_suspend: |
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if (!pm_runtime_status_suspended(&pdev->dev)) |
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tegra20_i2s_runtime_suspend(&pdev->dev); |
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err_pm_disable: |
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pm_runtime_disable(&pdev->dev); |
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err_clk_put: |
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clk_put(i2s->clk_i2s); |
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err: |
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return ret; |
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} |
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static int tegra20_i2s_platform_remove(struct platform_device *pdev) |
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{ |
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struct tegra20_i2s *i2s = dev_get_drvdata(&pdev->dev); |
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pm_runtime_disable(&pdev->dev); |
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if (!pm_runtime_status_suspended(&pdev->dev)) |
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tegra20_i2s_runtime_suspend(&pdev->dev); |
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tegra_pcm_platform_unregister(&pdev->dev); |
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snd_soc_unregister_component(&pdev->dev); |
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clk_put(i2s->clk_i2s); |
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return 0; |
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} |
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static const struct of_device_id tegra20_i2s_of_match[] = { |
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{ .compatible = "nvidia,tegra20-i2s", }, |
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{}, |
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}; |
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static const struct dev_pm_ops tegra20_i2s_pm_ops = { |
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SET_RUNTIME_PM_OPS(tegra20_i2s_runtime_suspend, |
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tegra20_i2s_runtime_resume, NULL) |
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}; |
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static struct platform_driver tegra20_i2s_driver = { |
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.driver = { |
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.name = DRV_NAME, |
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.of_match_table = tegra20_i2s_of_match, |
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.pm = &tegra20_i2s_pm_ops, |
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}, |
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.probe = tegra20_i2s_platform_probe, |
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.remove = tegra20_i2s_platform_remove, |
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}; |
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module_platform_driver(tegra20_i2s_driver); |
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MODULE_AUTHOR("Stephen Warren <[email protected]>"); |
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MODULE_DESCRIPTION("Tegra20 I2S ASoC driver"); |
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MODULE_LICENSE("GPL"); |
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MODULE_ALIAS("platform:" DRV_NAME); |
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MODULE_DEVICE_TABLE(of, tegra20_i2s_of_match);
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