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628 lines
14 KiB
628 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// |
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// Helper routines for R-Car sound ADG. |
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// |
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// Copyright (C) 2013 Kuninori Morimoto <[email protected]> |
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#include <linux/clk-provider.h> |
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#include "rsnd.h" |
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#define CLKA 0 |
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#define CLKB 1 |
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#define CLKC 2 |
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#define CLKI 3 |
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#define CLKMAX 4 |
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#define CLKOUT 0 |
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#define CLKOUT1 1 |
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#define CLKOUT2 2 |
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#define CLKOUT3 3 |
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#define CLKOUTMAX 4 |
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#define BRRx_MASK(x) (0x3FF & x) |
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static struct rsnd_mod_ops adg_ops = { |
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.name = "adg", |
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}; |
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struct rsnd_adg { |
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struct clk *clk[CLKMAX]; |
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struct clk *clkout[CLKOUTMAX]; |
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struct clk_onecell_data onecell; |
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struct rsnd_mod mod; |
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int clk_rate[CLKMAX]; |
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u32 flags; |
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u32 ckr; |
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u32 rbga; |
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u32 rbgb; |
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int rbga_rate_for_441khz; /* RBGA */ |
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int rbgb_rate_for_48khz; /* RBGB */ |
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}; |
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#define LRCLK_ASYNC (1 << 0) |
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#define AUDIO_OUT_48 (1 << 1) |
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#define for_each_rsnd_clk(pos, adg, i) \ |
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for (i = 0; \ |
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(i < CLKMAX) && \ |
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((pos) = adg->clk[i]); \ |
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i++) |
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#define for_each_rsnd_clkout(pos, adg, i) \ |
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for (i = 0; \ |
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(i < CLKOUTMAX) && \ |
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((pos) = adg->clkout[i]); \ |
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i++) |
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#define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg) |
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static const char * const clk_name[] = { |
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[CLKA] = "clk_a", |
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[CLKB] = "clk_b", |
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[CLKC] = "clk_c", |
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[CLKI] = "clk_i", |
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}; |
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static u32 rsnd_adg_calculate_rbgx(unsigned long div) |
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{ |
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int i, ratio; |
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if (!div) |
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return 0; |
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for (i = 3; i >= 0; i--) { |
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ratio = 2 << (i * 2); |
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if (0 == (div % ratio)) |
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return (u32)((i << 8) | ((div / ratio) - 1)); |
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} |
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return ~0; |
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} |
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static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io) |
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{ |
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struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io); |
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int id = rsnd_mod_id(ssi_mod); |
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int ws = id; |
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if (rsnd_ssi_is_pin_sharing(io)) { |
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switch (id) { |
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case 1: |
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case 2: |
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case 9: |
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ws = 0; |
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break; |
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case 4: |
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ws = 3; |
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break; |
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case 8: |
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ws = 7; |
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break; |
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} |
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} |
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return (0x6 + ws) << 8; |
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} |
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static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv, |
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struct rsnd_dai_stream *io, |
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unsigned int target_rate, |
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unsigned int *target_val, |
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unsigned int *target_en) |
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{ |
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv); |
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struct device *dev = rsnd_priv_to_dev(priv); |
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int idx, sel, div, step; |
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unsigned int val, en; |
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unsigned int min, diff; |
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unsigned int sel_rate[] = { |
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adg->clk_rate[CLKA], /* 0000: CLKA */ |
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adg->clk_rate[CLKB], /* 0001: CLKB */ |
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adg->clk_rate[CLKC], /* 0010: CLKC */ |
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adg->rbga_rate_for_441khz, /* 0011: RBGA */ |
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adg->rbgb_rate_for_48khz, /* 0100: RBGB */ |
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}; |
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min = ~0; |
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val = 0; |
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en = 0; |
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for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) { |
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idx = 0; |
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step = 2; |
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if (!sel_rate[sel]) |
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continue; |
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for (div = 2; div <= 98304; div += step) { |
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diff = abs(target_rate - sel_rate[sel] / div); |
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if (min > diff) { |
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val = (sel << 8) | idx; |
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min = diff; |
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en = 1 << (sel + 1); /* fixme */ |
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} |
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/* |
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* step of 0_0000 / 0_0001 / 0_1101 |
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* are out of order |
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*/ |
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if ((idx > 2) && (idx % 2)) |
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step *= 2; |
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if (idx == 0x1c) { |
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div += step; |
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step *= 2; |
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} |
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idx++; |
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} |
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} |
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if (min == ~0) { |
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dev_err(dev, "no Input clock\n"); |
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return; |
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} |
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*target_val = val; |
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if (target_en) |
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*target_en = en; |
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} |
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static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv, |
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struct rsnd_dai_stream *io, |
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unsigned int in_rate, |
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unsigned int out_rate, |
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u32 *in, u32 *out, u32 *en) |
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{ |
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struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io); |
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unsigned int target_rate; |
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u32 *target_val; |
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u32 _in; |
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u32 _out; |
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u32 _en; |
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/* default = SSI WS */ |
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_in = |
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_out = rsnd_adg_ssi_ws_timing_gen2(io); |
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target_rate = 0; |
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target_val = NULL; |
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_en = 0; |
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if (runtime->rate != in_rate) { |
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target_rate = out_rate; |
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target_val = &_out; |
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} else if (runtime->rate != out_rate) { |
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target_rate = in_rate; |
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target_val = &_in; |
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} |
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if (target_rate) |
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__rsnd_adg_get_timesel_ratio(priv, io, |
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target_rate, |
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target_val, &_en); |
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if (in) |
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*in = _in; |
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if (out) |
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*out = _out; |
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if (en) |
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*en = _en; |
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} |
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int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod, |
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struct rsnd_dai_stream *io) |
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{ |
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struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod); |
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv); |
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struct rsnd_mod *adg_mod = rsnd_mod_get(adg); |
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int id = rsnd_mod_id(cmd_mod); |
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int shift = (id % 2) ? 16 : 0; |
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u32 mask, val; |
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rsnd_adg_get_timesel_ratio(priv, io, |
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rsnd_src_get_in_rate(priv, io), |
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rsnd_src_get_out_rate(priv, io), |
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NULL, &val, NULL); |
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val = val << shift; |
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mask = 0x0f1f << shift; |
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rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val); |
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return 0; |
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} |
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int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod, |
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struct rsnd_dai_stream *io, |
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unsigned int in_rate, |
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unsigned int out_rate) |
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{ |
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struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod); |
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv); |
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struct rsnd_mod *adg_mod = rsnd_mod_get(adg); |
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u32 in, out; |
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u32 mask, en; |
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int id = rsnd_mod_id(src_mod); |
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int shift = (id % 2) ? 16 : 0; |
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rsnd_mod_confirm_src(src_mod); |
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rsnd_adg_get_timesel_ratio(priv, io, |
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in_rate, out_rate, |
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&in, &out, &en); |
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in = in << shift; |
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out = out << shift; |
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mask = 0x0f1f << shift; |
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rsnd_mod_bset(adg_mod, SRCIN_TIMSEL(id / 2), mask, in); |
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rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL(id / 2), mask, out); |
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if (en) |
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rsnd_mod_bset(adg_mod, DIV_EN, en, en); |
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return 0; |
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} |
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static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val) |
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{ |
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struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod); |
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv); |
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struct rsnd_mod *adg_mod = rsnd_mod_get(adg); |
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struct device *dev = rsnd_priv_to_dev(priv); |
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int id = rsnd_mod_id(ssi_mod); |
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int shift = (id % 4) * 8; |
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u32 mask = 0xFF << shift; |
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rsnd_mod_confirm_ssi(ssi_mod); |
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val = val << shift; |
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/* |
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* SSI 8 is not connected to ADG. |
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* it works with SSI 7 |
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*/ |
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if (id == 8) |
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return; |
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rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL(id / 4), mask, val); |
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dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val); |
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} |
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int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate) |
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{ |
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv); |
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struct clk *clk; |
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int i; |
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int sel_table[] = { |
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[CLKA] = 0x1, |
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[CLKB] = 0x2, |
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[CLKC] = 0x3, |
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[CLKI] = 0x0, |
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}; |
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/* |
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* find suitable clock from |
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* AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI. |
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*/ |
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for_each_rsnd_clk(clk, adg, i) { |
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if (rate == adg->clk_rate[i]) |
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return sel_table[i]; |
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} |
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/* |
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* find divided clock from BRGA/BRGB |
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*/ |
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if (rate == adg->rbga_rate_for_441khz) |
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return 0x10; |
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if (rate == adg->rbgb_rate_for_48khz) |
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return 0x20; |
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return -EIO; |
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} |
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int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod) |
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{ |
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rsnd_adg_set_ssi_clk(ssi_mod, 0); |
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return 0; |
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} |
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int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate) |
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{ |
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struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod); |
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv); |
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struct device *dev = rsnd_priv_to_dev(priv); |
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struct rsnd_mod *adg_mod = rsnd_mod_get(adg); |
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int data; |
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u32 ckr = 0; |
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data = rsnd_adg_clk_query(priv, rate); |
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if (data < 0) |
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return data; |
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rsnd_adg_set_ssi_clk(ssi_mod, data); |
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if (rsnd_flags_has(adg, LRCLK_ASYNC)) { |
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if (rsnd_flags_has(adg, AUDIO_OUT_48)) |
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ckr = 0x80000000; |
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} else { |
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if (0 == (rate % 8000)) |
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ckr = 0x80000000; |
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} |
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rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr); |
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rsnd_mod_write(adg_mod, BRRA, adg->rbga); |
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rsnd_mod_write(adg_mod, BRRB, adg->rbgb); |
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dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n", |
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(ckr) ? 'B' : 'A', |
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(ckr) ? adg->rbgb_rate_for_48khz : |
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adg->rbga_rate_for_441khz); |
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return 0; |
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} |
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void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable) |
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{ |
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv); |
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struct device *dev = rsnd_priv_to_dev(priv); |
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struct clk *clk; |
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int i; |
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for_each_rsnd_clk(clk, adg, i) { |
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if (enable) { |
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int ret = clk_prepare_enable(clk); |
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/* |
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* We shouldn't use clk_get_rate() under |
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* atomic context. Let's keep it when |
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* rsnd_adg_clk_enable() was called |
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*/ |
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adg->clk_rate[i] = 0; |
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if (ret < 0) |
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dev_warn(dev, "can't use clk %d\n", i); |
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else |
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adg->clk_rate[i] = clk_get_rate(clk); |
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} else { |
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if (adg->clk_rate[i]) |
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clk_disable_unprepare(clk); |
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adg->clk_rate[i] = 0; |
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} |
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} |
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} |
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static void rsnd_adg_get_clkin(struct rsnd_priv *priv, |
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struct rsnd_adg *adg) |
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{ |
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struct device *dev = rsnd_priv_to_dev(priv); |
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struct clk *clk; |
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int i; |
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for (i = 0; i < CLKMAX; i++) { |
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clk = devm_clk_get(dev, clk_name[i]); |
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adg->clk[i] = IS_ERR(clk) ? NULL : clk; |
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} |
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} |
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static void rsnd_adg_get_clkout(struct rsnd_priv *priv, |
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struct rsnd_adg *adg) |
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{ |
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struct clk *clk; |
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struct device *dev = rsnd_priv_to_dev(priv); |
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struct device_node *np = dev->of_node; |
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struct property *prop; |
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u32 ckr, rbgx, rbga, rbgb; |
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u32 rate, div; |
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#define REQ_SIZE 2 |
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u32 req_rate[REQ_SIZE] = {}; |
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uint32_t count = 0; |
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unsigned long req_48kHz_rate, req_441kHz_rate; |
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int i, req_size; |
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const char *parent_clk_name = NULL; |
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static const char * const clkout_name[] = { |
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[CLKOUT] = "audio_clkout", |
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[CLKOUT1] = "audio_clkout1", |
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[CLKOUT2] = "audio_clkout2", |
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[CLKOUT3] = "audio_clkout3", |
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}; |
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int brg_table[] = { |
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[CLKA] = 0x0, |
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[CLKB] = 0x1, |
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[CLKC] = 0x4, |
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[CLKI] = 0x2, |
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}; |
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ckr = 0; |
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rbga = 2; /* default 1/6 */ |
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rbgb = 2; /* default 1/6 */ |
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/* |
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* ADG supports BRRA/BRRB output only |
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* this means all clkout0/1/2/3 will be same rate |
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*/ |
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prop = of_find_property(np, "clock-frequency", NULL); |
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if (!prop) |
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goto rsnd_adg_get_clkout_end; |
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req_size = prop->length / sizeof(u32); |
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if (req_size > REQ_SIZE) { |
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dev_err(dev, |
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"too many clock-frequency, use top %d\n", REQ_SIZE); |
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req_size = REQ_SIZE; |
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} |
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of_property_read_u32_array(np, "clock-frequency", req_rate, req_size); |
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req_48kHz_rate = 0; |
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req_441kHz_rate = 0; |
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for (i = 0; i < req_size; i++) { |
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if (0 == (req_rate[i] % 44100)) |
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req_441kHz_rate = req_rate[i]; |
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if (0 == (req_rate[i] % 48000)) |
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req_48kHz_rate = req_rate[i]; |
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} |
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if (req_rate[0] % 48000 == 0) |
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rsnd_flags_set(adg, AUDIO_OUT_48); |
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if (of_get_property(np, "clkout-lr-asynchronous", NULL)) |
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rsnd_flags_set(adg, LRCLK_ASYNC); |
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/* |
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* This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC |
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* have 44.1kHz or 48kHz base clocks for now. |
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* |
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* SSI itself can divide parent clock by 1/1 - 1/16 |
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* see |
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* rsnd_adg_ssi_clk_try_start() |
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* rsnd_ssi_master_clk_start() |
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*/ |
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adg->rbga_rate_for_441khz = 0; |
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adg->rbgb_rate_for_48khz = 0; |
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for_each_rsnd_clk(clk, adg, i) { |
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rate = clk_get_rate(clk); |
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if (0 == rate) /* not used */ |
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continue; |
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/* RBGA */ |
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if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) { |
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div = 6; |
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if (req_441kHz_rate) |
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div = rate / req_441kHz_rate; |
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rbgx = rsnd_adg_calculate_rbgx(div); |
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if (BRRx_MASK(rbgx) == rbgx) { |
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rbga = rbgx; |
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adg->rbga_rate_for_441khz = rate / div; |
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ckr |= brg_table[i] << 20; |
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if (req_441kHz_rate && |
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!rsnd_flags_has(adg, AUDIO_OUT_48)) |
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parent_clk_name = __clk_get_name(clk); |
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} |
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} |
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/* RBGB */ |
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if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) { |
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div = 6; |
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if (req_48kHz_rate) |
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div = rate / req_48kHz_rate; |
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rbgx = rsnd_adg_calculate_rbgx(div); |
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if (BRRx_MASK(rbgx) == rbgx) { |
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rbgb = rbgx; |
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adg->rbgb_rate_for_48khz = rate / div; |
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ckr |= brg_table[i] << 16; |
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if (req_48kHz_rate && |
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rsnd_flags_has(adg, AUDIO_OUT_48)) |
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parent_clk_name = __clk_get_name(clk); |
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} |
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} |
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} |
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/* |
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* ADG supports BRRA/BRRB output only. |
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* this means all clkout0/1/2/3 will be * same rate |
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*/ |
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of_property_read_u32(np, "#clock-cells", &count); |
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/* |
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* for clkout |
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*/ |
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if (!count) { |
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clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT], |
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parent_clk_name, 0, req_rate[0]); |
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if (!IS_ERR(clk)) { |
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adg->clkout[CLKOUT] = clk; |
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of_clk_add_provider(np, of_clk_src_simple_get, clk); |
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} |
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} |
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/* |
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* for clkout0/1/2/3 |
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*/ |
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else { |
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for (i = 0; i < CLKOUTMAX; i++) { |
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clk = clk_register_fixed_rate(dev, clkout_name[i], |
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parent_clk_name, 0, |
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req_rate[0]); |
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if (!IS_ERR(clk)) |
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adg->clkout[i] = clk; |
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} |
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adg->onecell.clks = adg->clkout; |
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adg->onecell.clk_num = CLKOUTMAX; |
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of_clk_add_provider(np, of_clk_src_onecell_get, |
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&adg->onecell); |
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} |
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rsnd_adg_get_clkout_end: |
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adg->ckr = ckr; |
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adg->rbga = rbga; |
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adg->rbgb = rbgb; |
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} |
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#ifdef DEBUG |
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static void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct rsnd_adg *adg) |
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{ |
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struct device *dev = rsnd_priv_to_dev(priv); |
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struct clk *clk; |
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int i; |
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|
for_each_rsnd_clk(clk, adg, i) |
|
dev_dbg(dev, "%s : %pa : %ld\n", |
|
clk_name[i], clk, clk_get_rate(clk)); |
|
|
|
dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n", |
|
adg->ckr, adg->rbga, adg->rbgb); |
|
dev_dbg(dev, "BRGA (for 44100 base) = %d\n", adg->rbga_rate_for_441khz); |
|
dev_dbg(dev, "BRGB (for 48000 base) = %d\n", adg->rbgb_rate_for_48khz); |
|
|
|
/* |
|
* Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start() |
|
* by BRGCKR::BRGCKR_31 |
|
*/ |
|
for_each_rsnd_clkout(clk, adg, i) |
|
dev_dbg(dev, "clkout %d : %pa : %ld\n", i, |
|
clk, clk_get_rate(clk)); |
|
} |
|
#else |
|
#define rsnd_adg_clk_dbg_info(priv, adg) |
|
#endif |
|
|
|
int rsnd_adg_probe(struct rsnd_priv *priv) |
|
{ |
|
struct rsnd_adg *adg; |
|
struct device *dev = rsnd_priv_to_dev(priv); |
|
int ret; |
|
|
|
adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL); |
|
if (!adg) |
|
return -ENOMEM; |
|
|
|
ret = rsnd_mod_init(priv, &adg->mod, &adg_ops, |
|
NULL, 0, 0); |
|
if (ret) |
|
return ret; |
|
|
|
rsnd_adg_get_clkin(priv, adg); |
|
rsnd_adg_get_clkout(priv, adg); |
|
rsnd_adg_clk_dbg_info(priv, adg); |
|
|
|
priv->adg = adg; |
|
|
|
rsnd_adg_clk_enable(priv); |
|
|
|
return 0; |
|
} |
|
|
|
void rsnd_adg_remove(struct rsnd_priv *priv) |
|
{ |
|
struct device *dev = rsnd_priv_to_dev(priv); |
|
struct device_node *np = dev->of_node; |
|
struct rsnd_adg *adg = priv->adg; |
|
struct clk *clk; |
|
int i; |
|
|
|
for_each_rsnd_clkout(clk, adg, i) |
|
if (adg->clkout[i]) |
|
clk_unregister_fixed_rate(adg->clkout[i]); |
|
|
|
of_clk_del_provider(np); |
|
|
|
rsnd_adg_clk_disable(priv); |
|
}
|
|
|