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344 lines
7.9 KiB
344 lines
7.9 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// |
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// Hitachi Audio Controller (AC97) support for SH7760/SH7780 |
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// |
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// Copyright (c) 2007 Manuel Lauss <[email protected]> |
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// |
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// dont forget to set IPSEL/OMSEL register bits (in your board code) to |
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// enable HAC output pins! |
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/* BIG FAT FIXME: although the SH7760 has 2 independent AC97 units, only |
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* the FIRST can be used since ASoC does not pass any information to the |
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* ac97_read/write() functions regarding WHICH unit to use. You'll have |
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* to edit the code a bit to use the other AC97 unit. --mlau |
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*/ |
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#include <linux/init.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/interrupt.h> |
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#include <linux/wait.h> |
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#include <linux/delay.h> |
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#include <sound/core.h> |
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#include <sound/pcm.h> |
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#include <sound/ac97_codec.h> |
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#include <sound/initval.h> |
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#include <sound/soc.h> |
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/* regs and bits */ |
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#define HACCR 0x08 |
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#define HACCSAR 0x20 |
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#define HACCSDR 0x24 |
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#define HACPCML 0x28 |
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#define HACPCMR 0x2C |
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#define HACTIER 0x50 |
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#define HACTSR 0x54 |
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#define HACRIER 0x58 |
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#define HACRSR 0x5C |
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#define HACACR 0x60 |
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#define CR_CR (1 << 15) /* "codec-ready" indicator */ |
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#define CR_CDRT (1 << 11) /* cold reset */ |
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#define CR_WMRT (1 << 10) /* warm reset */ |
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#define CR_B9 (1 << 9) /* the mysterious "bit 9" */ |
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#define CR_ST (1 << 5) /* AC97 link start bit */ |
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#define CSAR_RD (1 << 19) /* AC97 data read bit */ |
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#define CSAR_WR (0) |
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#define TSR_CMDAMT (1 << 31) |
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#define TSR_CMDDMT (1 << 30) |
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#define RSR_STARY (1 << 22) |
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#define RSR_STDRY (1 << 21) |
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#define ACR_DMARX16 (1 << 30) |
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#define ACR_DMATX16 (1 << 29) |
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#define ACR_TX12ATOM (1 << 26) |
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#define ACR_DMARX20 ((1 << 24) | (1 << 22)) |
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#define ACR_DMATX20 ((1 << 23) | (1 << 21)) |
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#define CSDR_SHIFT 4 |
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#define CSDR_MASK (0xffff << CSDR_SHIFT) |
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#define CSAR_SHIFT 12 |
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#define CSAR_MASK (0x7f << CSAR_SHIFT) |
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#define AC97_WRITE_RETRY 1 |
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#define AC97_READ_RETRY 5 |
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/* manual-suggested AC97 codec access timeouts (us) */ |
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#define TMO_E1 500 /* 21 < E1 < 1000 */ |
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#define TMO_E2 13 /* 13 < E2 */ |
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#define TMO_E3 21 /* 21 < E3 */ |
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#define TMO_E4 500 /* 21 < E4 < 1000 */ |
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struct hac_priv { |
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unsigned long mmio; /* HAC base address */ |
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} hac_cpu_data[] = { |
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#if defined(CONFIG_CPU_SUBTYPE_SH7760) |
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{ |
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.mmio = 0xFE240000, |
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}, |
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{ |
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.mmio = 0xFE250000, |
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}, |
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#elif defined(CONFIG_CPU_SUBTYPE_SH7780) |
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{ |
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.mmio = 0xFFE40000, |
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}, |
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#else |
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#error "Unsupported SuperH SoC" |
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#endif |
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}; |
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#define HACREG(reg) (*(unsigned long *)(hac->mmio + (reg))) |
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/* |
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* AC97 read/write flow as outlined in the SH7760 manual (pages 903-906) |
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*/ |
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static int hac_get_codec_data(struct hac_priv *hac, unsigned short r, |
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unsigned short *v) |
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{ |
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unsigned int to1, to2, i; |
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unsigned short adr; |
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for (i = AC97_READ_RETRY; i; i--) { |
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*v = 0; |
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/* wait for HAC to receive something from the codec */ |
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for (to1 = TMO_E4; |
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to1 && !(HACREG(HACRSR) & RSR_STARY); |
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--to1) |
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udelay(1); |
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for (to2 = TMO_E4; |
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to2 && !(HACREG(HACRSR) & RSR_STDRY); |
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--to2) |
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udelay(1); |
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if (!to1 && !to2) |
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return 0; /* codec comm is down */ |
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adr = ((HACREG(HACCSAR) & CSAR_MASK) >> CSAR_SHIFT); |
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*v = ((HACREG(HACCSDR) & CSDR_MASK) >> CSDR_SHIFT); |
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HACREG(HACRSR) &= ~(RSR_STDRY | RSR_STARY); |
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if (r == adr) |
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break; |
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/* manual says: wait at least 21 usec before retrying */ |
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udelay(21); |
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} |
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HACREG(HACRSR) &= ~(RSR_STDRY | RSR_STARY); |
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return i; |
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} |
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static unsigned short hac_read_codec_aux(struct hac_priv *hac, |
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unsigned short reg) |
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{ |
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unsigned short val; |
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unsigned int i, to; |
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for (i = AC97_READ_RETRY; i; i--) { |
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/* send_read_request */ |
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local_irq_disable(); |
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HACREG(HACTSR) &= ~(TSR_CMDAMT); |
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HACREG(HACCSAR) = (reg << CSAR_SHIFT) | CSAR_RD; |
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local_irq_enable(); |
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for (to = TMO_E3; |
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to && !(HACREG(HACTSR) & TSR_CMDAMT); |
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--to) |
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udelay(1); |
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HACREG(HACTSR) &= ~TSR_CMDAMT; |
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val = 0; |
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if (hac_get_codec_data(hac, reg, &val) != 0) |
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break; |
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} |
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return i ? val : ~0; |
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} |
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static void hac_ac97_write(struct snd_ac97 *ac97, unsigned short reg, |
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unsigned short val) |
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{ |
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int unit_id = 0 /* ac97->private_data */; |
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struct hac_priv *hac = &hac_cpu_data[unit_id]; |
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unsigned int i, to; |
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/* write_codec_aux */ |
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for (i = AC97_WRITE_RETRY; i; i--) { |
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/* send_write_request */ |
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local_irq_disable(); |
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HACREG(HACTSR) &= ~(TSR_CMDDMT | TSR_CMDAMT); |
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HACREG(HACCSDR) = (val << CSDR_SHIFT); |
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HACREG(HACCSAR) = (reg << CSAR_SHIFT) & (~CSAR_RD); |
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local_irq_enable(); |
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/* poll-wait for CMDAMT and CMDDMT */ |
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for (to = TMO_E1; |
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to && !(HACREG(HACTSR) & (TSR_CMDAMT|TSR_CMDDMT)); |
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--to) |
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udelay(1); |
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HACREG(HACTSR) &= ~(TSR_CMDAMT | TSR_CMDDMT); |
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if (to) |
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break; |
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/* timeout, try again */ |
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} |
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} |
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static unsigned short hac_ac97_read(struct snd_ac97 *ac97, |
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unsigned short reg) |
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{ |
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int unit_id = 0 /* ac97->private_data */; |
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struct hac_priv *hac = &hac_cpu_data[unit_id]; |
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return hac_read_codec_aux(hac, reg); |
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} |
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static void hac_ac97_warmrst(struct snd_ac97 *ac97) |
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{ |
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int unit_id = 0 /* ac97->private_data */; |
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struct hac_priv *hac = &hac_cpu_data[unit_id]; |
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unsigned int tmo; |
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HACREG(HACCR) = CR_WMRT | CR_ST | CR_B9; |
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msleep(10); |
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HACREG(HACCR) = CR_ST | CR_B9; |
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for (tmo = 1000; (tmo > 0) && !(HACREG(HACCR) & CR_CR); tmo--) |
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udelay(1); |
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if (!tmo) |
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printk(KERN_INFO "hac: reset: AC97 link down!\n"); |
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/* settings this bit lets us have a conversation with codec */ |
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HACREG(HACACR) |= ACR_TX12ATOM; |
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} |
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static void hac_ac97_coldrst(struct snd_ac97 *ac97) |
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{ |
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int unit_id = 0 /* ac97->private_data */; |
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struct hac_priv *hac; |
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hac = &hac_cpu_data[unit_id]; |
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HACREG(HACCR) = 0; |
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HACREG(HACCR) = CR_CDRT | CR_ST | CR_B9; |
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msleep(10); |
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hac_ac97_warmrst(ac97); |
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} |
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static struct snd_ac97_bus_ops hac_ac97_ops = { |
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.read = hac_ac97_read, |
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.write = hac_ac97_write, |
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.reset = hac_ac97_coldrst, |
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.warm_reset = hac_ac97_warmrst, |
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}; |
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static int hac_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *dai) |
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{ |
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struct hac_priv *hac = &hac_cpu_data[dai->id]; |
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int d = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; |
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switch (params->msbits) { |
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case 16: |
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HACREG(HACACR) |= d ? ACR_DMARX16 : ACR_DMATX16; |
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HACREG(HACACR) &= d ? ~ACR_DMARX20 : ~ACR_DMATX20; |
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break; |
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case 20: |
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HACREG(HACACR) &= d ? ~ACR_DMARX16 : ~ACR_DMATX16; |
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HACREG(HACACR) |= d ? ACR_DMARX20 : ACR_DMATX20; |
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break; |
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default: |
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pr_debug("hac: invalid depth %d bit\n", params->msbits); |
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return -EINVAL; |
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break; |
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} |
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return 0; |
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} |
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#define AC97_RATES \ |
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SNDRV_PCM_RATE_8000_192000 |
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#define AC97_FMTS \ |
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SNDRV_PCM_FMTBIT_S16_LE |
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static const struct snd_soc_dai_ops hac_dai_ops = { |
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.hw_params = hac_hw_params, |
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}; |
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static struct snd_soc_dai_driver sh4_hac_dai[] = { |
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{ |
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.name = "hac-dai.0", |
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.playback = { |
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.rates = AC97_RATES, |
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.formats = AC97_FMTS, |
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.channels_min = 2, |
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.channels_max = 2, |
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}, |
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.capture = { |
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.rates = AC97_RATES, |
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.formats = AC97_FMTS, |
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.channels_min = 2, |
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.channels_max = 2, |
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}, |
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.ops = &hac_dai_ops, |
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}, |
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#ifdef CONFIG_CPU_SUBTYPE_SH7760 |
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{ |
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.name = "hac-dai.1", |
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.id = 1, |
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.playback = { |
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.rates = AC97_RATES, |
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.formats = AC97_FMTS, |
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.channels_min = 2, |
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.channels_max = 2, |
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}, |
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.capture = { |
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.rates = AC97_RATES, |
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.formats = AC97_FMTS, |
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.channels_min = 2, |
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.channels_max = 2, |
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}, |
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.ops = &hac_dai_ops, |
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}, |
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#endif |
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}; |
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static const struct snd_soc_component_driver sh4_hac_component = { |
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.name = "sh4-hac", |
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}; |
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static int hac_soc_platform_probe(struct platform_device *pdev) |
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{ |
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int ret; |
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ret = snd_soc_set_ac97_ops(&hac_ac97_ops); |
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if (ret != 0) |
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return ret; |
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return devm_snd_soc_register_component(&pdev->dev, &sh4_hac_component, |
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sh4_hac_dai, ARRAY_SIZE(sh4_hac_dai)); |
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} |
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static int hac_soc_platform_remove(struct platform_device *pdev) |
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{ |
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snd_soc_set_ac97_ops(NULL); |
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return 0; |
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} |
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static struct platform_driver hac_pcm_driver = { |
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.driver = { |
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.name = "hac-pcm-audio", |
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}, |
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.probe = hac_soc_platform_probe, |
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.remove = hac_soc_platform_remove, |
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}; |
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module_platform_driver(hac_pcm_driver); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_DESCRIPTION("SuperH onchip HAC (AC97) audio driver"); |
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MODULE_AUTHOR("Manuel Lauss <[email protected]>");
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