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464 lines
12 KiB
464 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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// |
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// s3c24xx-i2s.c -- ALSA Soc Audio Layer |
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// |
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// (c) 2006 Wolfson Microelectronics PLC. |
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// Graeme Gregory [email protected] or [email protected] |
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// |
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// Copyright 2004-2005 Simtec Electronics |
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// http://armlinux.simtec.co.uk/ |
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// Ben Dooks <[email protected]> |
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#include <linux/delay.h> |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/gpio.h> |
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#include <linux/module.h> |
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#include <sound/soc.h> |
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#include <sound/pcm_params.h> |
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#include "regs-iis.h" |
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#include "dma.h" |
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#include "s3c24xx-i2s.h" |
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static struct snd_dmaengine_dai_dma_data s3c24xx_i2s_pcm_stereo_out = { |
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.chan_name = "tx", |
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.addr_width = 2, |
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}; |
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static struct snd_dmaengine_dai_dma_data s3c24xx_i2s_pcm_stereo_in = { |
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.chan_name = "rx", |
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.addr_width = 2, |
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}; |
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struct s3c24xx_i2s_info { |
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void __iomem *regs; |
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struct clk *iis_clk; |
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u32 iiscon; |
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u32 iismod; |
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u32 iisfcon; |
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u32 iispsr; |
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}; |
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static struct s3c24xx_i2s_info s3c24xx_i2s; |
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static void s3c24xx_snd_txctrl(int on) |
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{ |
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u32 iisfcon; |
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u32 iiscon; |
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u32 iismod; |
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iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON); |
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iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON); |
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iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD); |
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pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon); |
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if (on) { |
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iisfcon |= S3C2410_IISFCON_TXDMA | S3C2410_IISFCON_TXENABLE; |
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iiscon |= S3C2410_IISCON_TXDMAEN | S3C2410_IISCON_IISEN; |
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iiscon &= ~S3C2410_IISCON_TXIDLE; |
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iismod |= S3C2410_IISMOD_TXMODE; |
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); |
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writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); |
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writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); |
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} else { |
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/* note, we have to disable the FIFOs otherwise bad things |
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* seem to happen when the DMA stops. According to the |
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* Samsung supplied kernel, this should allow the DMA |
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* engine and FIFOs to reset. If this isn't allowed, the |
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* DMA engine will simply freeze randomly. |
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*/ |
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iisfcon &= ~S3C2410_IISFCON_TXENABLE; |
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iisfcon &= ~S3C2410_IISFCON_TXDMA; |
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iiscon |= S3C2410_IISCON_TXIDLE; |
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iiscon &= ~S3C2410_IISCON_TXDMAEN; |
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iismod &= ~S3C2410_IISMOD_TXMODE; |
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writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); |
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writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); |
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); |
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} |
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pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon); |
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} |
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static void s3c24xx_snd_rxctrl(int on) |
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{ |
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u32 iisfcon; |
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u32 iiscon; |
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u32 iismod; |
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iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON); |
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iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON); |
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iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD); |
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pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon); |
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if (on) { |
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iisfcon |= S3C2410_IISFCON_RXDMA | S3C2410_IISFCON_RXENABLE; |
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iiscon |= S3C2410_IISCON_RXDMAEN | S3C2410_IISCON_IISEN; |
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iiscon &= ~S3C2410_IISCON_RXIDLE; |
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iismod |= S3C2410_IISMOD_RXMODE; |
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); |
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writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); |
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writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); |
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} else { |
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/* note, we have to disable the FIFOs otherwise bad things |
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* seem to happen when the DMA stops. According to the |
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* Samsung supplied kernel, this should allow the DMA |
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* engine and FIFOs to reset. If this isn't allowed, the |
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* DMA engine will simply freeze randomly. |
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*/ |
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iisfcon &= ~S3C2410_IISFCON_RXENABLE; |
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iisfcon &= ~S3C2410_IISFCON_RXDMA; |
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iiscon |= S3C2410_IISCON_RXIDLE; |
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iiscon &= ~S3C2410_IISCON_RXDMAEN; |
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iismod &= ~S3C2410_IISMOD_RXMODE; |
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writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); |
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writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); |
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); |
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} |
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pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon); |
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} |
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/* |
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* Wait for the LR signal to allow synchronisation to the L/R clock |
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* from the codec. May only be needed for slave mode. |
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*/ |
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static int s3c24xx_snd_lrsync(void) |
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{ |
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u32 iiscon; |
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int timeout = 50; /* 5ms */ |
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while (1) { |
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iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON); |
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if (iiscon & S3C2410_IISCON_LRINDEX) |
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break; |
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if (!timeout--) |
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return -ETIMEDOUT; |
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udelay(100); |
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} |
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return 0; |
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} |
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/* |
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* Check whether CPU is the master or slave |
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*/ |
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static inline int s3c24xx_snd_is_clkmaster(void) |
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{ |
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return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1; |
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} |
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/* |
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* Set S3C24xx I2S DAI format |
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*/ |
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static int s3c24xx_i2s_set_fmt(struct snd_soc_dai *cpu_dai, |
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unsigned int fmt) |
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{ |
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u32 iismod; |
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iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD); |
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pr_debug("hw_params r: IISMOD: %x \n", iismod); |
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
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case SND_SOC_DAIFMT_CBM_CFM: |
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iismod |= S3C2410_IISMOD_SLAVE; |
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break; |
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case SND_SOC_DAIFMT_CBS_CFS: |
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iismod &= ~S3C2410_IISMOD_SLAVE; |
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break; |
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default: |
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return -EINVAL; |
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} |
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
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case SND_SOC_DAIFMT_LEFT_J: |
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iismod |= S3C2410_IISMOD_MSB; |
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break; |
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case SND_SOC_DAIFMT_I2S: |
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iismod &= ~S3C2410_IISMOD_MSB; |
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break; |
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default: |
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return -EINVAL; |
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} |
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); |
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pr_debug("hw_params w: IISMOD: %x \n", iismod); |
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return 0; |
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} |
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static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *dai) |
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{ |
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struct snd_dmaengine_dai_dma_data *dma_data; |
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u32 iismod; |
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dma_data = snd_soc_dai_get_dma_data(dai, substream); |
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/* Working copies of register */ |
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iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD); |
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pr_debug("hw_params r: IISMOD: %x\n", iismod); |
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switch (params_width(params)) { |
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case 8: |
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iismod &= ~S3C2410_IISMOD_16BIT; |
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dma_data->addr_width = 1; |
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break; |
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case 16: |
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iismod |= S3C2410_IISMOD_16BIT; |
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dma_data->addr_width = 2; |
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break; |
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default: |
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return -EINVAL; |
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} |
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); |
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pr_debug("hw_params w: IISMOD: %x\n", iismod); |
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return 0; |
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} |
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static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd, |
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struct snd_soc_dai *dai) |
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{ |
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int ret = 0; |
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switch (cmd) { |
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case SNDRV_PCM_TRIGGER_START: |
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case SNDRV_PCM_TRIGGER_RESUME: |
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
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if (!s3c24xx_snd_is_clkmaster()) { |
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ret = s3c24xx_snd_lrsync(); |
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if (ret) |
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goto exit_err; |
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} |
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) |
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s3c24xx_snd_rxctrl(1); |
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else |
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s3c24xx_snd_txctrl(1); |
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break; |
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case SNDRV_PCM_TRIGGER_STOP: |
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case SNDRV_PCM_TRIGGER_SUSPEND: |
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) |
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s3c24xx_snd_rxctrl(0); |
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else |
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s3c24xx_snd_txctrl(0); |
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break; |
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default: |
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ret = -EINVAL; |
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break; |
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} |
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exit_err: |
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return ret; |
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} |
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/* |
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* Set S3C24xx Clock source |
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*/ |
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static int s3c24xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, |
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int clk_id, unsigned int freq, int dir) |
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{ |
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u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD); |
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iismod &= ~S3C2440_IISMOD_MPLL; |
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switch (clk_id) { |
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case S3C24XX_CLKSRC_PCLK: |
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break; |
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case S3C24XX_CLKSRC_MPLL: |
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iismod |= S3C2440_IISMOD_MPLL; |
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break; |
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default: |
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return -EINVAL; |
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} |
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); |
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return 0; |
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} |
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/* |
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* Set S3C24xx Clock dividers |
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*/ |
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static int s3c24xx_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai, |
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int div_id, int div) |
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{ |
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u32 reg; |
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switch (div_id) { |
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case S3C24XX_DIV_BCLK: |
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reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK; |
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writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD); |
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break; |
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case S3C24XX_DIV_MCLK: |
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reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS); |
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writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD); |
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break; |
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case S3C24XX_DIV_PRESCALER: |
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writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR); |
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reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON); |
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writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON); |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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/* |
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* To avoid duplicating clock code, allow machine driver to |
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* get the clockrate from here. |
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*/ |
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u32 s3c24xx_i2s_get_clockrate(void) |
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{ |
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return clk_get_rate(s3c24xx_i2s.iis_clk); |
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} |
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EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate); |
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static int s3c24xx_i2s_probe(struct snd_soc_dai *dai) |
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{ |
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int ret; |
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snd_soc_dai_init_dma_data(dai, &s3c24xx_i2s_pcm_stereo_out, |
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&s3c24xx_i2s_pcm_stereo_in); |
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s3c24xx_i2s.iis_clk = devm_clk_get(dai->dev, "iis"); |
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if (IS_ERR(s3c24xx_i2s.iis_clk)) { |
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pr_err("failed to get iis_clock\n"); |
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return PTR_ERR(s3c24xx_i2s.iis_clk); |
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} |
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ret = clk_prepare_enable(s3c24xx_i2s.iis_clk); |
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if (ret) |
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return ret; |
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writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON); |
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s3c24xx_snd_txctrl(0); |
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s3c24xx_snd_rxctrl(0); |
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return 0; |
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} |
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#ifdef CONFIG_PM |
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static int s3c24xx_i2s_suspend(struct snd_soc_component *component) |
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{ |
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s3c24xx_i2s.iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON); |
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s3c24xx_i2s.iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD); |
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s3c24xx_i2s.iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON); |
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s3c24xx_i2s.iispsr = readl(s3c24xx_i2s.regs + S3C2410_IISPSR); |
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clk_disable_unprepare(s3c24xx_i2s.iis_clk); |
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return 0; |
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} |
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static int s3c24xx_i2s_resume(struct snd_soc_component *component) |
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{ |
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int ret; |
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ret = clk_prepare_enable(s3c24xx_i2s.iis_clk); |
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if (ret) |
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return ret; |
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writel(s3c24xx_i2s.iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); |
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writel(s3c24xx_i2s.iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); |
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writel(s3c24xx_i2s.iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); |
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writel(s3c24xx_i2s.iispsr, s3c24xx_i2s.regs + S3C2410_IISPSR); |
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return 0; |
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} |
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#else |
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#define s3c24xx_i2s_suspend NULL |
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#define s3c24xx_i2s_resume NULL |
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#endif |
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#define S3C24XX_I2S_RATES \ |
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(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \ |
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SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ |
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SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) |
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static const struct snd_soc_dai_ops s3c24xx_i2s_dai_ops = { |
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.trigger = s3c24xx_i2s_trigger, |
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.hw_params = s3c24xx_i2s_hw_params, |
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.set_fmt = s3c24xx_i2s_set_fmt, |
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.set_clkdiv = s3c24xx_i2s_set_clkdiv, |
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.set_sysclk = s3c24xx_i2s_set_sysclk, |
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}; |
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static struct snd_soc_dai_driver s3c24xx_i2s_dai = { |
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.probe = s3c24xx_i2s_probe, |
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.playback = { |
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.channels_min = 2, |
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.channels_max = 2, |
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.rates = S3C24XX_I2S_RATES, |
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.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,}, |
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.capture = { |
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.channels_min = 2, |
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.channels_max = 2, |
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.rates = S3C24XX_I2S_RATES, |
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.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,}, |
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.ops = &s3c24xx_i2s_dai_ops, |
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}; |
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static const struct snd_soc_component_driver s3c24xx_i2s_component = { |
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.name = "s3c24xx-i2s", |
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.suspend = s3c24xx_i2s_suspend, |
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.resume = s3c24xx_i2s_resume, |
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}; |
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static int s3c24xx_iis_dev_probe(struct platform_device *pdev) |
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{ |
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struct resource *res; |
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int ret; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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s3c24xx_i2s.regs = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(s3c24xx_i2s.regs)) |
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return PTR_ERR(s3c24xx_i2s.regs); |
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s3c24xx_i2s_pcm_stereo_out.addr = res->start + S3C2410_IISFIFO; |
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s3c24xx_i2s_pcm_stereo_in.addr = res->start + S3C2410_IISFIFO; |
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ret = samsung_asoc_dma_platform_register(&pdev->dev, NULL, |
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"tx", "rx", NULL); |
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if (ret) { |
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dev_err(&pdev->dev, "Failed to register the DMA: %d\n", ret); |
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return ret; |
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} |
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ret = devm_snd_soc_register_component(&pdev->dev, |
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&s3c24xx_i2s_component, &s3c24xx_i2s_dai, 1); |
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if (ret) |
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dev_err(&pdev->dev, "Failed to register the DAI\n"); |
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return ret; |
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} |
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static struct platform_driver s3c24xx_iis_driver = { |
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.probe = s3c24xx_iis_dev_probe, |
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.driver = { |
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.name = "s3c24xx-iis", |
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}, |
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}; |
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module_platform_driver(s3c24xx_iis_driver); |
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/* Module information */ |
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MODULE_AUTHOR("Ben Dooks, <[email protected]>"); |
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MODULE_DESCRIPTION("s3c24xx I2S SoC Interface"); |
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MODULE_LICENSE("GPL"); |
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MODULE_ALIAS("platform:s3c24xx-iis");
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