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607 lines
15 KiB
607 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// |
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// ALSA SoC Audio Layer - S3C PCM-Controller driver |
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// |
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// Copyright (c) 2009 Samsung Electronics Co. Ltd |
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// Author: Jaswinder Singh <[email protected]> |
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// based upon I2S drivers by Ben Dooks. |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/pm_runtime.h> |
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#include <sound/soc.h> |
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#include <sound/pcm_params.h> |
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#include <linux/platform_data/asoc-s3c.h> |
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#include "dma.h" |
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#include "pcm.h" |
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/*Register Offsets */ |
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#define S3C_PCM_CTL 0x00 |
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#define S3C_PCM_CLKCTL 0x04 |
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#define S3C_PCM_TXFIFO 0x08 |
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#define S3C_PCM_RXFIFO 0x0C |
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#define S3C_PCM_IRQCTL 0x10 |
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#define S3C_PCM_IRQSTAT 0x14 |
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#define S3C_PCM_FIFOSTAT 0x18 |
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#define S3C_PCM_CLRINT 0x20 |
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/* PCM_CTL Bit-Fields */ |
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#define S3C_PCM_CTL_TXDIPSTICK_MASK 0x3f |
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#define S3C_PCM_CTL_TXDIPSTICK_SHIFT 13 |
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#define S3C_PCM_CTL_RXDIPSTICK_MASK 0x3f |
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#define S3C_PCM_CTL_RXDIPSTICK_SHIFT 7 |
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#define S3C_PCM_CTL_TXDMA_EN (0x1 << 6) |
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#define S3C_PCM_CTL_RXDMA_EN (0x1 << 5) |
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#define S3C_PCM_CTL_TXMSB_AFTER_FSYNC (0x1 << 4) |
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#define S3C_PCM_CTL_RXMSB_AFTER_FSYNC (0x1 << 3) |
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#define S3C_PCM_CTL_TXFIFO_EN (0x1 << 2) |
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#define S3C_PCM_CTL_RXFIFO_EN (0x1 << 1) |
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#define S3C_PCM_CTL_ENABLE (0x1 << 0) |
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/* PCM_CLKCTL Bit-Fields */ |
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#define S3C_PCM_CLKCTL_SERCLK_EN (0x1 << 19) |
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#define S3C_PCM_CLKCTL_SERCLKSEL_PCLK (0x1 << 18) |
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#define S3C_PCM_CLKCTL_SCLKDIV_MASK 0x1ff |
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#define S3C_PCM_CLKCTL_SYNCDIV_MASK 0x1ff |
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#define S3C_PCM_CLKCTL_SCLKDIV_SHIFT 9 |
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#define S3C_PCM_CLKCTL_SYNCDIV_SHIFT 0 |
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/* PCM_TXFIFO Bit-Fields */ |
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#define S3C_PCM_TXFIFO_DVALID (0x1 << 16) |
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#define S3C_PCM_TXFIFO_DATA_MSK (0xffff << 0) |
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/* PCM_RXFIFO Bit-Fields */ |
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#define S3C_PCM_RXFIFO_DVALID (0x1 << 16) |
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#define S3C_PCM_RXFIFO_DATA_MSK (0xffff << 0) |
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/* PCM_IRQCTL Bit-Fields */ |
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#define S3C_PCM_IRQCTL_IRQEN (0x1 << 14) |
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#define S3C_PCM_IRQCTL_WRDEN (0x1 << 12) |
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#define S3C_PCM_IRQCTL_TXEMPTYEN (0x1 << 11) |
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#define S3C_PCM_IRQCTL_TXALMSTEMPTYEN (0x1 << 10) |
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#define S3C_PCM_IRQCTL_TXFULLEN (0x1 << 9) |
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#define S3C_PCM_IRQCTL_TXALMSTFULLEN (0x1 << 8) |
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#define S3C_PCM_IRQCTL_TXSTARVEN (0x1 << 7) |
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#define S3C_PCM_IRQCTL_TXERROVRFLEN (0x1 << 6) |
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#define S3C_PCM_IRQCTL_RXEMPTEN (0x1 << 5) |
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#define S3C_PCM_IRQCTL_RXALMSTEMPTEN (0x1 << 4) |
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#define S3C_PCM_IRQCTL_RXFULLEN (0x1 << 3) |
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#define S3C_PCM_IRQCTL_RXALMSTFULLEN (0x1 << 2) |
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#define S3C_PCM_IRQCTL_RXSTARVEN (0x1 << 1) |
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#define S3C_PCM_IRQCTL_RXERROVRFLEN (0x1 << 0) |
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/* PCM_IRQSTAT Bit-Fields */ |
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#define S3C_PCM_IRQSTAT_IRQPND (0x1 << 13) |
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#define S3C_PCM_IRQSTAT_WRD_XFER (0x1 << 12) |
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#define S3C_PCM_IRQSTAT_TXEMPTY (0x1 << 11) |
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#define S3C_PCM_IRQSTAT_TXALMSTEMPTY (0x1 << 10) |
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#define S3C_PCM_IRQSTAT_TXFULL (0x1 << 9) |
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#define S3C_PCM_IRQSTAT_TXALMSTFULL (0x1 << 8) |
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#define S3C_PCM_IRQSTAT_TXSTARV (0x1 << 7) |
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#define S3C_PCM_IRQSTAT_TXERROVRFL (0x1 << 6) |
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#define S3C_PCM_IRQSTAT_RXEMPT (0x1 << 5) |
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#define S3C_PCM_IRQSTAT_RXALMSTEMPT (0x1 << 4) |
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#define S3C_PCM_IRQSTAT_RXFULL (0x1 << 3) |
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#define S3C_PCM_IRQSTAT_RXALMSTFULL (0x1 << 2) |
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#define S3C_PCM_IRQSTAT_RXSTARV (0x1 << 1) |
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#define S3C_PCM_IRQSTAT_RXERROVRFL (0x1 << 0) |
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/* PCM_FIFOSTAT Bit-Fields */ |
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#define S3C_PCM_FIFOSTAT_TXCNT_MSK (0x3f << 14) |
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#define S3C_PCM_FIFOSTAT_TXFIFOEMPTY (0x1 << 13) |
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#define S3C_PCM_FIFOSTAT_TXFIFOALMSTEMPTY (0x1 << 12) |
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#define S3C_PCM_FIFOSTAT_TXFIFOFULL (0x1 << 11) |
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#define S3C_PCM_FIFOSTAT_TXFIFOALMSTFULL (0x1 << 10) |
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#define S3C_PCM_FIFOSTAT_RXCNT_MSK (0x3f << 4) |
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#define S3C_PCM_FIFOSTAT_RXFIFOEMPTY (0x1 << 3) |
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#define S3C_PCM_FIFOSTAT_RXFIFOALMSTEMPTY (0x1 << 2) |
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#define S3C_PCM_FIFOSTAT_RXFIFOFULL (0x1 << 1) |
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#define S3C_PCM_FIFOSTAT_RXFIFOALMSTFULL (0x1 << 0) |
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/** |
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* struct s3c_pcm_info - S3C PCM Controller information |
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* @lock: Spin lock |
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* @dev: The parent device passed to use from the probe. |
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* @regs: The pointer to the device register block. |
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* @sclk_per_fs: number of sclk per frame sync |
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* @idleclk: Whether to keep PCMSCLK enabled even when idle (no active xfer) |
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* @pclk: the PCLK_PCM (pcm) clock pointer |
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* @cclk: the SCLK_AUDIO (audio-bus) clock pointer |
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* @dma_playback: DMA information for playback channel. |
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* @dma_capture: DMA information for capture channel. |
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*/ |
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struct s3c_pcm_info { |
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spinlock_t lock; |
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struct device *dev; |
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void __iomem *regs; |
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unsigned int sclk_per_fs; |
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/* Whether to keep PCMSCLK enabled even when idle(no active xfer) */ |
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unsigned int idleclk; |
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struct clk *pclk; |
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struct clk *cclk; |
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struct snd_dmaengine_dai_dma_data *dma_playback; |
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struct snd_dmaengine_dai_dma_data *dma_capture; |
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}; |
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static struct snd_dmaengine_dai_dma_data s3c_pcm_stereo_out[] = { |
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[0] = { |
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.addr_width = 4, |
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}, |
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[1] = { |
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.addr_width = 4, |
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}, |
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}; |
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static struct snd_dmaengine_dai_dma_data s3c_pcm_stereo_in[] = { |
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[0] = { |
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.addr_width = 4, |
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}, |
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[1] = { |
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.addr_width = 4, |
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}, |
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}; |
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static struct s3c_pcm_info s3c_pcm[2]; |
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static void s3c_pcm_snd_txctrl(struct s3c_pcm_info *pcm, int on) |
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{ |
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void __iomem *regs = pcm->regs; |
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u32 ctl, clkctl; |
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clkctl = readl(regs + S3C_PCM_CLKCTL); |
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ctl = readl(regs + S3C_PCM_CTL); |
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ctl &= ~(S3C_PCM_CTL_TXDIPSTICK_MASK |
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<< S3C_PCM_CTL_TXDIPSTICK_SHIFT); |
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if (on) { |
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ctl |= S3C_PCM_CTL_TXDMA_EN; |
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ctl |= S3C_PCM_CTL_TXFIFO_EN; |
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ctl |= S3C_PCM_CTL_ENABLE; |
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ctl |= (0x4<<S3C_PCM_CTL_TXDIPSTICK_SHIFT); |
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clkctl |= S3C_PCM_CLKCTL_SERCLK_EN; |
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} else { |
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ctl &= ~S3C_PCM_CTL_TXDMA_EN; |
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ctl &= ~S3C_PCM_CTL_TXFIFO_EN; |
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if (!(ctl & S3C_PCM_CTL_RXFIFO_EN)) { |
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ctl &= ~S3C_PCM_CTL_ENABLE; |
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if (!pcm->idleclk) |
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clkctl |= S3C_PCM_CLKCTL_SERCLK_EN; |
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} |
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} |
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writel(clkctl, regs + S3C_PCM_CLKCTL); |
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writel(ctl, regs + S3C_PCM_CTL); |
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} |
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static void s3c_pcm_snd_rxctrl(struct s3c_pcm_info *pcm, int on) |
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{ |
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void __iomem *regs = pcm->regs; |
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u32 ctl, clkctl; |
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ctl = readl(regs + S3C_PCM_CTL); |
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clkctl = readl(regs + S3C_PCM_CLKCTL); |
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ctl &= ~(S3C_PCM_CTL_RXDIPSTICK_MASK |
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<< S3C_PCM_CTL_RXDIPSTICK_SHIFT); |
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if (on) { |
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ctl |= S3C_PCM_CTL_RXDMA_EN; |
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ctl |= S3C_PCM_CTL_RXFIFO_EN; |
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ctl |= S3C_PCM_CTL_ENABLE; |
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ctl |= (0x20<<S3C_PCM_CTL_RXDIPSTICK_SHIFT); |
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clkctl |= S3C_PCM_CLKCTL_SERCLK_EN; |
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} else { |
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ctl &= ~S3C_PCM_CTL_RXDMA_EN; |
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ctl &= ~S3C_PCM_CTL_RXFIFO_EN; |
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if (!(ctl & S3C_PCM_CTL_TXFIFO_EN)) { |
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ctl &= ~S3C_PCM_CTL_ENABLE; |
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if (!pcm->idleclk) |
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clkctl |= S3C_PCM_CLKCTL_SERCLK_EN; |
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} |
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} |
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writel(clkctl, regs + S3C_PCM_CLKCTL); |
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writel(ctl, regs + S3C_PCM_CTL); |
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} |
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static int s3c_pcm_trigger(struct snd_pcm_substream *substream, int cmd, |
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struct snd_soc_dai *dai) |
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{ |
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struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); |
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struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); |
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unsigned long flags; |
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dev_dbg(pcm->dev, "Entered %s\n", __func__); |
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switch (cmd) { |
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case SNDRV_PCM_TRIGGER_START: |
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case SNDRV_PCM_TRIGGER_RESUME: |
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
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spin_lock_irqsave(&pcm->lock, flags); |
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) |
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s3c_pcm_snd_rxctrl(pcm, 1); |
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else |
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s3c_pcm_snd_txctrl(pcm, 1); |
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spin_unlock_irqrestore(&pcm->lock, flags); |
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break; |
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case SNDRV_PCM_TRIGGER_STOP: |
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case SNDRV_PCM_TRIGGER_SUSPEND: |
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
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spin_lock_irqsave(&pcm->lock, flags); |
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) |
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s3c_pcm_snd_rxctrl(pcm, 0); |
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else |
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s3c_pcm_snd_txctrl(pcm, 0); |
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spin_unlock_irqrestore(&pcm->lock, flags); |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int s3c_pcm_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *socdai) |
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{ |
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struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); |
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struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); |
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void __iomem *regs = pcm->regs; |
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struct clk *clk; |
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int sclk_div, sync_div; |
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unsigned long flags; |
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u32 clkctl; |
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dev_dbg(pcm->dev, "Entered %s\n", __func__); |
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/* Strictly check for sample size */ |
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switch (params_width(params)) { |
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case 16: |
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break; |
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default: |
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return -EINVAL; |
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} |
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spin_lock_irqsave(&pcm->lock, flags); |
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/* Get hold of the PCMSOURCE_CLK */ |
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clkctl = readl(regs + S3C_PCM_CLKCTL); |
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if (clkctl & S3C_PCM_CLKCTL_SERCLKSEL_PCLK) |
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clk = pcm->pclk; |
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else |
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clk = pcm->cclk; |
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/* Set the SCLK divider */ |
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sclk_div = clk_get_rate(clk) / pcm->sclk_per_fs / |
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params_rate(params) / 2 - 1; |
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clkctl &= ~(S3C_PCM_CLKCTL_SCLKDIV_MASK |
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<< S3C_PCM_CLKCTL_SCLKDIV_SHIFT); |
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clkctl |= ((sclk_div & S3C_PCM_CLKCTL_SCLKDIV_MASK) |
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<< S3C_PCM_CLKCTL_SCLKDIV_SHIFT); |
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/* Set the SYNC divider */ |
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sync_div = pcm->sclk_per_fs - 1; |
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clkctl &= ~(S3C_PCM_CLKCTL_SYNCDIV_MASK |
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<< S3C_PCM_CLKCTL_SYNCDIV_SHIFT); |
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clkctl |= ((sync_div & S3C_PCM_CLKCTL_SYNCDIV_MASK) |
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<< S3C_PCM_CLKCTL_SYNCDIV_SHIFT); |
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writel(clkctl, regs + S3C_PCM_CLKCTL); |
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spin_unlock_irqrestore(&pcm->lock, flags); |
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dev_dbg(pcm->dev, "PCMSOURCE_CLK-%lu SCLK=%ufs SCLK_DIV=%d SYNC_DIV=%d\n", |
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clk_get_rate(clk), pcm->sclk_per_fs, |
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sclk_div, sync_div); |
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return 0; |
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} |
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static int s3c_pcm_set_fmt(struct snd_soc_dai *cpu_dai, |
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unsigned int fmt) |
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{ |
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struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai); |
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void __iomem *regs = pcm->regs; |
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unsigned long flags; |
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int ret = 0; |
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u32 ctl; |
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dev_dbg(pcm->dev, "Entered %s\n", __func__); |
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spin_lock_irqsave(&pcm->lock, flags); |
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ctl = readl(regs + S3C_PCM_CTL); |
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
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case SND_SOC_DAIFMT_IB_NF: |
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/* Nothing to do, IB_NF by default */ |
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break; |
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default: |
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dev_err(pcm->dev, "Unsupported clock inversion!\n"); |
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ret = -EINVAL; |
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goto exit; |
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} |
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
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case SND_SOC_DAIFMT_CBS_CFS: |
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/* Nothing to do, Master by default */ |
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break; |
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default: |
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dev_err(pcm->dev, "Unsupported master/slave format!\n"); |
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ret = -EINVAL; |
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goto exit; |
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} |
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switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) { |
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case SND_SOC_DAIFMT_CONT: |
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pcm->idleclk = 1; |
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break; |
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case SND_SOC_DAIFMT_GATED: |
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pcm->idleclk = 0; |
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break; |
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default: |
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dev_err(pcm->dev, "Invalid Clock gating request!\n"); |
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ret = -EINVAL; |
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goto exit; |
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} |
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
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case SND_SOC_DAIFMT_DSP_A: |
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ctl |= S3C_PCM_CTL_TXMSB_AFTER_FSYNC; |
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ctl |= S3C_PCM_CTL_RXMSB_AFTER_FSYNC; |
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break; |
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case SND_SOC_DAIFMT_DSP_B: |
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ctl &= ~S3C_PCM_CTL_TXMSB_AFTER_FSYNC; |
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ctl &= ~S3C_PCM_CTL_RXMSB_AFTER_FSYNC; |
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break; |
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default: |
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dev_err(pcm->dev, "Unsupported data format!\n"); |
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ret = -EINVAL; |
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goto exit; |
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} |
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writel(ctl, regs + S3C_PCM_CTL); |
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exit: |
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spin_unlock_irqrestore(&pcm->lock, flags); |
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return ret; |
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} |
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static int s3c_pcm_set_clkdiv(struct snd_soc_dai *cpu_dai, |
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int div_id, int div) |
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{ |
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struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai); |
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switch (div_id) { |
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case S3C_PCM_SCLK_PER_FS: |
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pcm->sclk_per_fs = div; |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int s3c_pcm_set_sysclk(struct snd_soc_dai *cpu_dai, |
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int clk_id, unsigned int freq, int dir) |
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{ |
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struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai); |
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void __iomem *regs = pcm->regs; |
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u32 clkctl = readl(regs + S3C_PCM_CLKCTL); |
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switch (clk_id) { |
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case S3C_PCM_CLKSRC_PCLK: |
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clkctl |= S3C_PCM_CLKCTL_SERCLKSEL_PCLK; |
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break; |
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case S3C_PCM_CLKSRC_MUX: |
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clkctl &= ~S3C_PCM_CLKCTL_SERCLKSEL_PCLK; |
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if (clk_get_rate(pcm->cclk) != freq) |
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clk_set_rate(pcm->cclk, freq); |
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break; |
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default: |
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return -EINVAL; |
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} |
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writel(clkctl, regs + S3C_PCM_CLKCTL); |
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return 0; |
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} |
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static const struct snd_soc_dai_ops s3c_pcm_dai_ops = { |
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.set_sysclk = s3c_pcm_set_sysclk, |
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.set_clkdiv = s3c_pcm_set_clkdiv, |
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.trigger = s3c_pcm_trigger, |
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.hw_params = s3c_pcm_hw_params, |
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.set_fmt = s3c_pcm_set_fmt, |
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}; |
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static int s3c_pcm_dai_probe(struct snd_soc_dai *dai) |
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{ |
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struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(dai); |
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snd_soc_dai_init_dma_data(dai, pcm->dma_playback, pcm->dma_capture); |
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return 0; |
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} |
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#define S3C_PCM_RATES SNDRV_PCM_RATE_8000_96000 |
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#define S3C_PCM_DAI_DECLARE \ |
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.symmetric_rate = 1, \ |
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.probe = s3c_pcm_dai_probe, \ |
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.ops = &s3c_pcm_dai_ops, \ |
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.playback = { \ |
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.channels_min = 2, \ |
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.channels_max = 2, \ |
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.rates = S3C_PCM_RATES, \ |
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.formats = SNDRV_PCM_FMTBIT_S16_LE, \ |
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}, \ |
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.capture = { \ |
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.channels_min = 2, \ |
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.channels_max = 2, \ |
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.rates = S3C_PCM_RATES, \ |
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.formats = SNDRV_PCM_FMTBIT_S16_LE, \ |
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} |
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static struct snd_soc_dai_driver s3c_pcm_dai[] = { |
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[0] = { |
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.name = "samsung-pcm.0", |
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S3C_PCM_DAI_DECLARE, |
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}, |
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[1] = { |
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.name = "samsung-pcm.1", |
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S3C_PCM_DAI_DECLARE, |
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}, |
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}; |
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static const struct snd_soc_component_driver s3c_pcm_component = { |
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.name = "s3c-pcm", |
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}; |
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static int s3c_pcm_dev_probe(struct platform_device *pdev) |
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{ |
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struct s3c_pcm_info *pcm; |
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struct resource *mem_res; |
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struct s3c_audio_pdata *pcm_pdata; |
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dma_filter_fn filter; |
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int ret; |
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/* Check for valid device index */ |
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if ((pdev->id < 0) || pdev->id >= ARRAY_SIZE(s3c_pcm)) { |
|
dev_err(&pdev->dev, "id %d out of range\n", pdev->id); |
|
return -EINVAL; |
|
} |
|
|
|
pcm_pdata = pdev->dev.platform_data; |
|
|
|
if (pcm_pdata && pcm_pdata->cfg_gpio && pcm_pdata->cfg_gpio(pdev)) { |
|
dev_err(&pdev->dev, "Unable to configure gpio\n"); |
|
return -EINVAL; |
|
} |
|
|
|
pcm = &s3c_pcm[pdev->id]; |
|
pcm->dev = &pdev->dev; |
|
|
|
spin_lock_init(&pcm->lock); |
|
|
|
/* Default is 128fs */ |
|
pcm->sclk_per_fs = 128; |
|
|
|
mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
pcm->regs = devm_ioremap_resource(&pdev->dev, mem_res); |
|
if (IS_ERR(pcm->regs)) |
|
return PTR_ERR(pcm->regs); |
|
|
|
pcm->cclk = devm_clk_get(&pdev->dev, "audio-bus"); |
|
if (IS_ERR(pcm->cclk)) { |
|
dev_err(&pdev->dev, "failed to get audio-bus clock\n"); |
|
return PTR_ERR(pcm->cclk); |
|
} |
|
ret = clk_prepare_enable(pcm->cclk); |
|
if (ret) |
|
return ret; |
|
|
|
/* record our pcm structure for later use in the callbacks */ |
|
dev_set_drvdata(&pdev->dev, pcm); |
|
|
|
pcm->pclk = devm_clk_get(&pdev->dev, "pcm"); |
|
if (IS_ERR(pcm->pclk)) { |
|
dev_err(&pdev->dev, "failed to get pcm clock\n"); |
|
ret = PTR_ERR(pcm->pclk); |
|
goto err_dis_cclk; |
|
} |
|
ret = clk_prepare_enable(pcm->pclk); |
|
if (ret) |
|
goto err_dis_cclk; |
|
|
|
s3c_pcm_stereo_in[pdev->id].addr = mem_res->start + S3C_PCM_RXFIFO; |
|
s3c_pcm_stereo_out[pdev->id].addr = mem_res->start + S3C_PCM_TXFIFO; |
|
|
|
filter = NULL; |
|
if (pcm_pdata) { |
|
s3c_pcm_stereo_in[pdev->id].filter_data = pcm_pdata->dma_capture; |
|
s3c_pcm_stereo_out[pdev->id].filter_data = pcm_pdata->dma_playback; |
|
filter = pcm_pdata->dma_filter; |
|
} |
|
|
|
pcm->dma_capture = &s3c_pcm_stereo_in[pdev->id]; |
|
pcm->dma_playback = &s3c_pcm_stereo_out[pdev->id]; |
|
|
|
ret = samsung_asoc_dma_platform_register(&pdev->dev, filter, |
|
NULL, NULL, NULL); |
|
if (ret) { |
|
dev_err(&pdev->dev, "failed to get register DMA: %d\n", ret); |
|
goto err_dis_pclk; |
|
} |
|
|
|
pm_runtime_enable(&pdev->dev); |
|
|
|
ret = devm_snd_soc_register_component(&pdev->dev, &s3c_pcm_component, |
|
&s3c_pcm_dai[pdev->id], 1); |
|
if (ret != 0) { |
|
dev_err(&pdev->dev, "failed to get register DAI: %d\n", ret); |
|
goto err_dis_pm; |
|
} |
|
|
|
return 0; |
|
|
|
err_dis_pm: |
|
pm_runtime_disable(&pdev->dev); |
|
err_dis_pclk: |
|
clk_disable_unprepare(pcm->pclk); |
|
err_dis_cclk: |
|
clk_disable_unprepare(pcm->cclk); |
|
return ret; |
|
} |
|
|
|
static int s3c_pcm_dev_remove(struct platform_device *pdev) |
|
{ |
|
struct s3c_pcm_info *pcm = &s3c_pcm[pdev->id]; |
|
|
|
pm_runtime_disable(&pdev->dev); |
|
clk_disable_unprepare(pcm->cclk); |
|
clk_disable_unprepare(pcm->pclk); |
|
|
|
return 0; |
|
} |
|
|
|
static struct platform_driver s3c_pcm_driver = { |
|
.probe = s3c_pcm_dev_probe, |
|
.remove = s3c_pcm_dev_remove, |
|
.driver = { |
|
.name = "samsung-pcm", |
|
}, |
|
}; |
|
|
|
module_platform_driver(s3c_pcm_driver); |
|
|
|
/* Module information */ |
|
MODULE_AUTHOR("Jaswinder Singh, <[email protected]>"); |
|
MODULE_DESCRIPTION("S3C PCM Controller Driver"); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_ALIAS("platform:samsung-pcm");
|
|
|