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652 lines
17 KiB
652 lines
17 KiB
// SPDX-License-Identifier: (GPL-2.0 OR MIT) |
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// |
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// Copyright (c) 2018 BayLibre, SAS. |
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// Author: Jerome Brunet <[email protected]> |
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#include <linux/clk.h> |
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#include <linux/module.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_platform.h> |
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#include <linux/regmap.h> |
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#include <sound/soc.h> |
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#include <sound/soc-dai.h> |
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#include <sound/pcm_params.h> |
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#define PDM_CTRL 0x00 |
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#define PDM_CTRL_EN BIT(31) |
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#define PDM_CTRL_OUT_MODE BIT(29) |
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#define PDM_CTRL_BYPASS_MODE BIT(28) |
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#define PDM_CTRL_RST_FIFO BIT(16) |
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#define PDM_CTRL_CHAN_RSTN_MASK GENMASK(15, 8) |
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#define PDM_CTRL_CHAN_RSTN(x) ((x) << 8) |
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#define PDM_CTRL_CHAN_EN_MASK GENMASK(7, 0) |
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#define PDM_CTRL_CHAN_EN(x) ((x) << 0) |
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#define PDM_HCIC_CTRL1 0x04 |
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#define PDM_FILTER_EN BIT(31) |
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#define PDM_HCIC_CTRL1_GAIN_SFT_MASK GENMASK(29, 24) |
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#define PDM_HCIC_CTRL1_GAIN_SFT(x) ((x) << 24) |
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#define PDM_HCIC_CTRL1_GAIN_MULT_MASK GENMASK(23, 16) |
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#define PDM_HCIC_CTRL1_GAIN_MULT(x) ((x) << 16) |
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#define PDM_HCIC_CTRL1_DSR_MASK GENMASK(8, 4) |
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#define PDM_HCIC_CTRL1_DSR(x) ((x) << 4) |
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#define PDM_HCIC_CTRL1_STAGE_NUM_MASK GENMASK(3, 0) |
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#define PDM_HCIC_CTRL1_STAGE_NUM(x) ((x) << 0) |
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#define PDM_HCIC_CTRL2 0x08 |
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#define PDM_F1_CTRL 0x0c |
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#define PDM_LPF_ROUND_MODE_MASK GENMASK(17, 16) |
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#define PDM_LPF_ROUND_MODE(x) ((x) << 16) |
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#define PDM_LPF_DSR_MASK GENMASK(15, 12) |
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#define PDM_LPF_DSR(x) ((x) << 12) |
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#define PDM_LPF_STAGE_NUM_MASK GENMASK(8, 0) |
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#define PDM_LPF_STAGE_NUM(x) ((x) << 0) |
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#define PDM_LPF_MAX_STAGE 336 |
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#define PDM_LPF_NUM 3 |
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#define PDM_F2_CTRL 0x10 |
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#define PDM_F3_CTRL 0x14 |
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#define PDM_HPF_CTRL 0x18 |
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#define PDM_HPF_SFT_STEPS_MASK GENMASK(20, 16) |
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#define PDM_HPF_SFT_STEPS(x) ((x) << 16) |
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#define PDM_HPF_OUT_FACTOR_MASK GENMASK(15, 0) |
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#define PDM_HPF_OUT_FACTOR(x) ((x) << 0) |
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#define PDM_CHAN_CTRL 0x1c |
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#define PDM_CHAN_CTRL_POINTER_WIDTH 8 |
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#define PDM_CHAN_CTRL_POINTER_MAX ((1 << PDM_CHAN_CTRL_POINTER_WIDTH) - 1) |
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#define PDM_CHAN_CTRL_NUM 4 |
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#define PDM_CHAN_CTRL1 0x20 |
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#define PDM_COEFF_ADDR 0x24 |
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#define PDM_COEFF_DATA 0x28 |
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#define PDM_CLKG_CTRL 0x2c |
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#define PDM_STS 0x30 |
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struct axg_pdm_lpf { |
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unsigned int ds; |
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unsigned int round_mode; |
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const unsigned int *tap; |
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unsigned int tap_num; |
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}; |
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struct axg_pdm_hcic { |
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unsigned int shift; |
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unsigned int mult; |
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unsigned int steps; |
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unsigned int ds; |
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}; |
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struct axg_pdm_hpf { |
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unsigned int out_factor; |
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unsigned int steps; |
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}; |
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struct axg_pdm_filters { |
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struct axg_pdm_hcic hcic; |
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struct axg_pdm_hpf hpf; |
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struct axg_pdm_lpf lpf[PDM_LPF_NUM]; |
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}; |
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struct axg_pdm_cfg { |
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const struct axg_pdm_filters *filters; |
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unsigned int sys_rate; |
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}; |
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struct axg_pdm { |
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const struct axg_pdm_cfg *cfg; |
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struct regmap *map; |
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struct clk *dclk; |
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struct clk *sysclk; |
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struct clk *pclk; |
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}; |
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static void axg_pdm_enable(struct regmap *map) |
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{ |
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/* Reset AFIFO */ |
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regmap_update_bits(map, PDM_CTRL, PDM_CTRL_RST_FIFO, PDM_CTRL_RST_FIFO); |
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regmap_update_bits(map, PDM_CTRL, PDM_CTRL_RST_FIFO, 0); |
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/* Enable PDM */ |
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regmap_update_bits(map, PDM_CTRL, PDM_CTRL_EN, PDM_CTRL_EN); |
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} |
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static void axg_pdm_disable(struct regmap *map) |
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{ |
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regmap_update_bits(map, PDM_CTRL, PDM_CTRL_EN, 0); |
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} |
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static void axg_pdm_filters_enable(struct regmap *map, bool enable) |
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{ |
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unsigned int val = enable ? PDM_FILTER_EN : 0; |
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regmap_update_bits(map, PDM_HCIC_CTRL1, PDM_FILTER_EN, val); |
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regmap_update_bits(map, PDM_F1_CTRL, PDM_FILTER_EN, val); |
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regmap_update_bits(map, PDM_F2_CTRL, PDM_FILTER_EN, val); |
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regmap_update_bits(map, PDM_F3_CTRL, PDM_FILTER_EN, val); |
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regmap_update_bits(map, PDM_HPF_CTRL, PDM_FILTER_EN, val); |
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} |
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static int axg_pdm_trigger(struct snd_pcm_substream *substream, int cmd, |
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struct snd_soc_dai *dai) |
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{ |
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struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai); |
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switch (cmd) { |
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case SNDRV_PCM_TRIGGER_START: |
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case SNDRV_PCM_TRIGGER_RESUME: |
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
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axg_pdm_enable(priv->map); |
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return 0; |
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case SNDRV_PCM_TRIGGER_STOP: |
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case SNDRV_PCM_TRIGGER_SUSPEND: |
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
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axg_pdm_disable(priv->map); |
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return 0; |
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default: |
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return -EINVAL; |
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} |
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} |
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static unsigned int axg_pdm_get_os(struct axg_pdm *priv) |
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{ |
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const struct axg_pdm_filters *filters = priv->cfg->filters; |
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unsigned int os = filters->hcic.ds; |
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int i; |
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/* |
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* The global oversampling factor is defined by the down sampling |
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* factor applied by each filter (HCIC and LPFs) |
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*/ |
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for (i = 0; i < PDM_LPF_NUM; i++) |
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os *= filters->lpf[i].ds; |
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return os; |
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} |
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static int axg_pdm_set_sysclk(struct axg_pdm *priv, unsigned int os, |
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unsigned int rate) |
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{ |
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unsigned int sys_rate = os * 2 * rate * PDM_CHAN_CTRL_POINTER_MAX; |
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/* |
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* Set the default system clock rate unless it is too fast for |
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* for the requested sample rate. In this case, the sample pointer |
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* counter could overflow so set a lower system clock rate |
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*/ |
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if (sys_rate < priv->cfg->sys_rate) |
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return clk_set_rate(priv->sysclk, sys_rate); |
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return clk_set_rate(priv->sysclk, priv->cfg->sys_rate); |
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} |
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static int axg_pdm_set_sample_pointer(struct axg_pdm *priv) |
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{ |
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unsigned int spmax, sp, val; |
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int i; |
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/* Max sample counter value per half period of dclk */ |
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spmax = DIV_ROUND_UP_ULL((u64)clk_get_rate(priv->sysclk), |
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clk_get_rate(priv->dclk) * 2); |
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/* Check if sysclk is not too fast - should not happen */ |
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if (WARN_ON(spmax > PDM_CHAN_CTRL_POINTER_MAX)) |
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return -EINVAL; |
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/* Capture the data when we are at 75% of the half period */ |
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sp = spmax * 3 / 4; |
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for (i = 0, val = 0; i < PDM_CHAN_CTRL_NUM; i++) |
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val |= sp << (PDM_CHAN_CTRL_POINTER_WIDTH * i); |
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regmap_write(priv->map, PDM_CHAN_CTRL, val); |
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regmap_write(priv->map, PDM_CHAN_CTRL1, val); |
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return 0; |
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} |
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static void axg_pdm_set_channel_mask(struct axg_pdm *priv, |
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unsigned int channels) |
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{ |
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unsigned int mask = GENMASK(channels - 1, 0); |
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/* Put all channel in reset */ |
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regmap_update_bits(priv->map, PDM_CTRL, |
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PDM_CTRL_CHAN_RSTN_MASK, 0); |
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/* Take the necessary channels out of reset and enable them */ |
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regmap_update_bits(priv->map, PDM_CTRL, |
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PDM_CTRL_CHAN_RSTN_MASK | |
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PDM_CTRL_CHAN_EN_MASK, |
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PDM_CTRL_CHAN_RSTN(mask) | |
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PDM_CTRL_CHAN_EN(mask)); |
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} |
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static int axg_pdm_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *dai) |
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{ |
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struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai); |
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unsigned int os = axg_pdm_get_os(priv); |
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unsigned int rate = params_rate(params); |
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unsigned int val; |
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int ret; |
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switch (params_width(params)) { |
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case 24: |
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val = PDM_CTRL_OUT_MODE; |
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break; |
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case 32: |
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val = 0; |
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break; |
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default: |
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dev_err(dai->dev, "unsupported sample width\n"); |
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return -EINVAL; |
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} |
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regmap_update_bits(priv->map, PDM_CTRL, PDM_CTRL_OUT_MODE, val); |
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ret = axg_pdm_set_sysclk(priv, os, rate); |
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if (ret) { |
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dev_err(dai->dev, "failed to set system clock\n"); |
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return ret; |
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} |
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ret = clk_set_rate(priv->dclk, rate * os); |
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if (ret) { |
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dev_err(dai->dev, "failed to set dclk\n"); |
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return ret; |
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} |
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ret = axg_pdm_set_sample_pointer(priv); |
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if (ret) { |
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dev_err(dai->dev, "invalid clock setting\n"); |
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return ret; |
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} |
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axg_pdm_set_channel_mask(priv, params_channels(params)); |
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return 0; |
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} |
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static int axg_pdm_startup(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai); |
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int ret; |
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ret = clk_prepare_enable(priv->dclk); |
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if (ret) { |
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dev_err(dai->dev, "enabling dclk failed\n"); |
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return ret; |
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} |
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/* Enable the filters */ |
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axg_pdm_filters_enable(priv->map, true); |
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return ret; |
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} |
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static void axg_pdm_shutdown(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai); |
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axg_pdm_filters_enable(priv->map, false); |
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clk_disable_unprepare(priv->dclk); |
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} |
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static const struct snd_soc_dai_ops axg_pdm_dai_ops = { |
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.trigger = axg_pdm_trigger, |
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.hw_params = axg_pdm_hw_params, |
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.startup = axg_pdm_startup, |
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.shutdown = axg_pdm_shutdown, |
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}; |
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static void axg_pdm_set_hcic_ctrl(struct axg_pdm *priv) |
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{ |
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const struct axg_pdm_hcic *hcic = &priv->cfg->filters->hcic; |
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unsigned int val; |
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val = PDM_HCIC_CTRL1_STAGE_NUM(hcic->steps); |
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val |= PDM_HCIC_CTRL1_DSR(hcic->ds); |
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val |= PDM_HCIC_CTRL1_GAIN_MULT(hcic->mult); |
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val |= PDM_HCIC_CTRL1_GAIN_SFT(hcic->shift); |
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regmap_update_bits(priv->map, PDM_HCIC_CTRL1, |
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PDM_HCIC_CTRL1_STAGE_NUM_MASK | |
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PDM_HCIC_CTRL1_DSR_MASK | |
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PDM_HCIC_CTRL1_GAIN_MULT_MASK | |
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PDM_HCIC_CTRL1_GAIN_SFT_MASK, |
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val); |
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} |
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static void axg_pdm_set_lpf_ctrl(struct axg_pdm *priv, unsigned int index) |
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{ |
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const struct axg_pdm_lpf *lpf = &priv->cfg->filters->lpf[index]; |
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unsigned int offset = index * regmap_get_reg_stride(priv->map) |
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+ PDM_F1_CTRL; |
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unsigned int val; |
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val = PDM_LPF_STAGE_NUM(lpf->tap_num); |
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val |= PDM_LPF_DSR(lpf->ds); |
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val |= PDM_LPF_ROUND_MODE(lpf->round_mode); |
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regmap_update_bits(priv->map, offset, |
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PDM_LPF_STAGE_NUM_MASK | |
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PDM_LPF_DSR_MASK | |
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PDM_LPF_ROUND_MODE_MASK, |
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val); |
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} |
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static void axg_pdm_set_hpf_ctrl(struct axg_pdm *priv) |
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{ |
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const struct axg_pdm_hpf *hpf = &priv->cfg->filters->hpf; |
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unsigned int val; |
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val = PDM_HPF_OUT_FACTOR(hpf->out_factor); |
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val |= PDM_HPF_SFT_STEPS(hpf->steps); |
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regmap_update_bits(priv->map, PDM_HPF_CTRL, |
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PDM_HPF_OUT_FACTOR_MASK | |
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PDM_HPF_SFT_STEPS_MASK, |
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val); |
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} |
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static int axg_pdm_set_lpf_filters(struct axg_pdm *priv) |
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{ |
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const struct axg_pdm_lpf *lpf = priv->cfg->filters->lpf; |
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unsigned int count = 0; |
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int i, j; |
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for (i = 0; i < PDM_LPF_NUM; i++) |
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count += lpf[i].tap_num; |
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/* Make sure the coeffs fit in the memory */ |
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if (count >= PDM_LPF_MAX_STAGE) |
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return -EINVAL; |
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/* Set the initial APB bus register address */ |
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regmap_write(priv->map, PDM_COEFF_ADDR, 0); |
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/* Set the tap filter values of all 3 filters */ |
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for (i = 0; i < PDM_LPF_NUM; i++) { |
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axg_pdm_set_lpf_ctrl(priv, i); |
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for (j = 0; j < lpf[i].tap_num; j++) |
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regmap_write(priv->map, PDM_COEFF_DATA, lpf[i].tap[j]); |
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} |
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return 0; |
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} |
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static int axg_pdm_dai_probe(struct snd_soc_dai *dai) |
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{ |
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struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai); |
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int ret; |
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ret = clk_prepare_enable(priv->pclk); |
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if (ret) { |
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dev_err(dai->dev, "enabling pclk failed\n"); |
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return ret; |
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} |
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/* |
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* sysclk must be set and enabled as well to access the pdm registers |
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* Accessing the register w/o it will give a bus error. |
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*/ |
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ret = clk_set_rate(priv->sysclk, priv->cfg->sys_rate); |
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if (ret) { |
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dev_err(dai->dev, "setting sysclk failed\n"); |
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goto err_pclk; |
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} |
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ret = clk_prepare_enable(priv->sysclk); |
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if (ret) { |
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dev_err(dai->dev, "enabling sysclk failed\n"); |
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goto err_pclk; |
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} |
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/* Make sure the device is initially disabled */ |
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axg_pdm_disable(priv->map); |
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/* Make sure filter bypass is disabled */ |
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regmap_update_bits(priv->map, PDM_CTRL, PDM_CTRL_BYPASS_MODE, 0); |
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/* Load filter settings */ |
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axg_pdm_set_hcic_ctrl(priv); |
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axg_pdm_set_hpf_ctrl(priv); |
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ret = axg_pdm_set_lpf_filters(priv); |
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if (ret) { |
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dev_err(dai->dev, "invalid filter configuration\n"); |
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goto err_sysclk; |
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} |
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return 0; |
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err_sysclk: |
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clk_disable_unprepare(priv->sysclk); |
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err_pclk: |
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clk_disable_unprepare(priv->pclk); |
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return ret; |
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} |
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static int axg_pdm_dai_remove(struct snd_soc_dai *dai) |
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{ |
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struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai); |
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clk_disable_unprepare(priv->sysclk); |
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clk_disable_unprepare(priv->pclk); |
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return 0; |
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} |
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static struct snd_soc_dai_driver axg_pdm_dai_drv = { |
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.name = "PDM", |
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.capture = { |
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.stream_name = "Capture", |
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.channels_min = 1, |
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.channels_max = 8, |
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.rates = SNDRV_PCM_RATE_CONTINUOUS, |
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.rate_min = 5512, |
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.rate_max = 48000, |
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.formats = (SNDRV_PCM_FMTBIT_S24_LE | |
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SNDRV_PCM_FMTBIT_S32_LE), |
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}, |
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.ops = &axg_pdm_dai_ops, |
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.probe = axg_pdm_dai_probe, |
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.remove = axg_pdm_dai_remove, |
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}; |
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static const struct snd_soc_component_driver axg_pdm_component_drv = {}; |
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static const struct regmap_config axg_pdm_regmap_cfg = { |
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.reg_bits = 32, |
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.val_bits = 32, |
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.reg_stride = 4, |
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.max_register = PDM_STS, |
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}; |
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static const unsigned int lpf1_default_tap[] = { |
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0x000014, 0xffffb2, 0xfffed9, 0xfffdce, 0xfffd45, |
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0xfffe32, 0x000147, 0x000645, 0x000b86, 0x000e21, |
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0x000ae3, 0x000000, 0xffeece, 0xffdca8, 0xffd212, |
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0xffd7d1, 0xfff2a7, 0x001f4c, 0x0050c2, 0x0072aa, |
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0x006ff1, 0x003c32, 0xffdc4e, 0xff6a18, 0xff0fef, |
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0xfefbaf, 0xff4c40, 0x000000, 0x00ebc8, 0x01c077, |
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0x02209e, 0x01c1a4, 0x008e60, 0xfebe52, 0xfcd690, |
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0xfb8fa5, 0xfba498, 0xfd9812, 0x0181ce, 0x06f5f3, |
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0x0d112f, 0x12a958, 0x169686, 0x18000e, 0x169686, |
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0x12a958, 0x0d112f, 0x06f5f3, 0x0181ce, 0xfd9812, |
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0xfba498, 0xfb8fa5, 0xfcd690, 0xfebe52, 0x008e60, |
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0x01c1a4, 0x02209e, 0x01c077, 0x00ebc8, 0x000000, |
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0xff4c40, 0xfefbaf, 0xff0fef, 0xff6a18, 0xffdc4e, |
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0x003c32, 0x006ff1, 0x0072aa, 0x0050c2, 0x001f4c, |
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0xfff2a7, 0xffd7d1, 0xffd212, 0xffdca8, 0xffeece, |
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0x000000, 0x000ae3, 0x000e21, 0x000b86, 0x000645, |
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0x000147, 0xfffe32, 0xfffd45, 0xfffdce, 0xfffed9, |
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0xffffb2, 0x000014, |
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}; |
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static const unsigned int lpf2_default_tap[] = { |
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0x00050a, 0xfff004, 0x0002c1, 0x003c12, 0xffa818, |
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0xffc87d, 0x010aef, 0xff5223, 0xfebd93, 0x028f41, |
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0xff5c0e, 0xfc63f8, 0x055f81, 0x000000, 0xf478a0, |
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0x11c5e3, 0x2ea74d, 0x11c5e3, 0xf478a0, 0x000000, |
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0x055f81, 0xfc63f8, 0xff5c0e, 0x028f41, 0xfebd93, |
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0xff5223, 0x010aef, 0xffc87d, 0xffa818, 0x003c12, |
|
0x0002c1, 0xfff004, 0x00050a, |
|
}; |
|
|
|
static const unsigned int lpf3_default_tap[] = { |
|
0x000000, 0x000081, 0x000000, 0xfffedb, 0x000000, |
|
0x00022d, 0x000000, 0xfffc46, 0x000000, 0x0005f7, |
|
0x000000, 0xfff6eb, 0x000000, 0x000d4e, 0x000000, |
|
0xffed1e, 0x000000, 0x001a1c, 0x000000, 0xffdcb0, |
|
0x000000, 0x002ede, 0x000000, 0xffc2d1, 0x000000, |
|
0x004ebe, 0x000000, 0xff9beb, 0x000000, 0x007dd7, |
|
0x000000, 0xff633a, 0x000000, 0x00c1d2, 0x000000, |
|
0xff11d5, 0x000000, 0x012368, 0x000000, 0xfe9c45, |
|
0x000000, 0x01b252, 0x000000, 0xfdebf6, 0x000000, |
|
0x0290b8, 0x000000, 0xfcca0d, 0x000000, 0x041d7c, |
|
0x000000, 0xfa8152, 0x000000, 0x07e9c6, 0x000000, |
|
0xf28fb5, 0x000000, 0x28b216, 0x3fffde, 0x28b216, |
|
0x000000, 0xf28fb5, 0x000000, 0x07e9c6, 0x000000, |
|
0xfa8152, 0x000000, 0x041d7c, 0x000000, 0xfcca0d, |
|
0x000000, 0x0290b8, 0x000000, 0xfdebf6, 0x000000, |
|
0x01b252, 0x000000, 0xfe9c45, 0x000000, 0x012368, |
|
0x000000, 0xff11d5, 0x000000, 0x00c1d2, 0x000000, |
|
0xff633a, 0x000000, 0x007dd7, 0x000000, 0xff9beb, |
|
0x000000, 0x004ebe, 0x000000, 0xffc2d1, 0x000000, |
|
0x002ede, 0x000000, 0xffdcb0, 0x000000, 0x001a1c, |
|
0x000000, 0xffed1e, 0x000000, 0x000d4e, 0x000000, |
|
0xfff6eb, 0x000000, 0x0005f7, 0x000000, 0xfffc46, |
|
0x000000, 0x00022d, 0x000000, 0xfffedb, 0x000000, |
|
0x000081, 0x000000, |
|
}; |
|
|
|
/* |
|
* These values are sane defaults for the axg platform: |
|
* - OS = 64 |
|
* - Latency = 38700 (?) |
|
* |
|
* TODO: There is a lot of different HCIC, LPFs and HPF configurations possible. |
|
* the configuration may depend on the dmic used by the platform, the |
|
* expected tradeoff between latency and quality, etc ... If/When other |
|
* settings are required, we should add a fw interface to this driver to |
|
* load new filter settings. |
|
*/ |
|
static const struct axg_pdm_filters axg_default_filters = { |
|
.hcic = { |
|
.shift = 0x15, |
|
.mult = 0x80, |
|
.steps = 7, |
|
.ds = 8, |
|
}, |
|
.hpf = { |
|
.out_factor = 0x8000, |
|
.steps = 13, |
|
}, |
|
.lpf = { |
|
[0] = { |
|
.ds = 2, |
|
.round_mode = 1, |
|
.tap = lpf1_default_tap, |
|
.tap_num = ARRAY_SIZE(lpf1_default_tap), |
|
}, |
|
[1] = { |
|
.ds = 2, |
|
.round_mode = 0, |
|
.tap = lpf2_default_tap, |
|
.tap_num = ARRAY_SIZE(lpf2_default_tap), |
|
}, |
|
[2] = { |
|
.ds = 2, |
|
.round_mode = 1, |
|
.tap = lpf3_default_tap, |
|
.tap_num = ARRAY_SIZE(lpf3_default_tap) |
|
}, |
|
}, |
|
}; |
|
|
|
static const struct axg_pdm_cfg axg_pdm_config = { |
|
.filters = &axg_default_filters, |
|
.sys_rate = 250000000, |
|
}; |
|
|
|
static const struct of_device_id axg_pdm_of_match[] = { |
|
{ |
|
.compatible = "amlogic,axg-pdm", |
|
.data = &axg_pdm_config, |
|
}, {} |
|
}; |
|
MODULE_DEVICE_TABLE(of, axg_pdm_of_match); |
|
|
|
static int axg_pdm_probe(struct platform_device *pdev) |
|
{ |
|
struct device *dev = &pdev->dev; |
|
struct axg_pdm *priv; |
|
void __iomem *regs; |
|
int ret; |
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
|
if (!priv) |
|
return -ENOMEM; |
|
platform_set_drvdata(pdev, priv); |
|
|
|
priv->cfg = of_device_get_match_data(dev); |
|
if (!priv->cfg) { |
|
dev_err(dev, "failed to match device\n"); |
|
return -ENODEV; |
|
} |
|
|
|
regs = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(regs)) |
|
return PTR_ERR(regs); |
|
|
|
priv->map = devm_regmap_init_mmio(dev, regs, &axg_pdm_regmap_cfg); |
|
if (IS_ERR(priv->map)) { |
|
dev_err(dev, "failed to init regmap: %ld\n", |
|
PTR_ERR(priv->map)); |
|
return PTR_ERR(priv->map); |
|
} |
|
|
|
priv->pclk = devm_clk_get(dev, "pclk"); |
|
if (IS_ERR(priv->pclk)) { |
|
ret = PTR_ERR(priv->pclk); |
|
if (ret != -EPROBE_DEFER) |
|
dev_err(dev, "failed to get pclk: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
priv->dclk = devm_clk_get(dev, "dclk"); |
|
if (IS_ERR(priv->dclk)) { |
|
ret = PTR_ERR(priv->dclk); |
|
if (ret != -EPROBE_DEFER) |
|
dev_err(dev, "failed to get dclk: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
priv->sysclk = devm_clk_get(dev, "sysclk"); |
|
if (IS_ERR(priv->sysclk)) { |
|
ret = PTR_ERR(priv->sysclk); |
|
if (ret != -EPROBE_DEFER) |
|
dev_err(dev, "failed to get dclk: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
return devm_snd_soc_register_component(dev, &axg_pdm_component_drv, |
|
&axg_pdm_dai_drv, 1); |
|
} |
|
|
|
static struct platform_driver axg_pdm_pdrv = { |
|
.probe = axg_pdm_probe, |
|
.driver = { |
|
.name = "axg-pdm", |
|
.of_match_table = axg_pdm_of_match, |
|
}, |
|
}; |
|
module_platform_driver(axg_pdm_pdrv); |
|
|
|
MODULE_DESCRIPTION("Amlogic AXG PDM Input driver"); |
|
MODULE_AUTHOR("Jerome Brunet <[email protected]>"); |
|
MODULE_LICENSE("GPL v2");
|
|
|