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364 lines
9.3 KiB
364 lines
9.3 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// |
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// Copyright (c) 2020 BayLibre, SAS. |
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// Author: Jerome Brunet <[email protected]> |
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#include <linux/bitfield.h> |
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#include <linux/clk.h> |
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#include <sound/pcm_params.h> |
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#include <sound/soc.h> |
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#include <sound/soc-dai.h> |
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#include "aiu.h" |
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#define AIU_I2S_SOURCE_DESC_MODE_8CH BIT(0) |
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#define AIU_I2S_SOURCE_DESC_MODE_24BIT BIT(5) |
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#define AIU_I2S_SOURCE_DESC_MODE_32BIT BIT(9) |
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#define AIU_I2S_SOURCE_DESC_MODE_SPLIT BIT(11) |
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#define AIU_RST_SOFT_I2S_FAST BIT(0) |
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#define AIU_I2S_DAC_CFG_MSB_FIRST BIT(2) |
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#define AIU_I2S_MISC_HOLD_EN BIT(2) |
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#define AIU_CLK_CTRL_I2S_DIV_EN BIT(0) |
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#define AIU_CLK_CTRL_I2S_DIV GENMASK(3, 2) |
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#define AIU_CLK_CTRL_AOCLK_INVERT BIT(6) |
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#define AIU_CLK_CTRL_LRCLK_INVERT BIT(7) |
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#define AIU_CLK_CTRL_LRCLK_SKEW GENMASK(9, 8) |
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#define AIU_CLK_CTRL_MORE_HDMI_AMCLK BIT(6) |
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#define AIU_CLK_CTRL_MORE_I2S_DIV GENMASK(5, 0) |
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#define AIU_CODEC_DAC_LRCLK_CTRL_DIV GENMASK(11, 0) |
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static void aiu_encoder_i2s_divider_enable(struct snd_soc_component *component, |
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bool enable) |
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{ |
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snd_soc_component_update_bits(component, AIU_CLK_CTRL, |
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AIU_CLK_CTRL_I2S_DIV_EN, |
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enable ? AIU_CLK_CTRL_I2S_DIV_EN : 0); |
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} |
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static void aiu_encoder_i2s_hold(struct snd_soc_component *component, |
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bool enable) |
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{ |
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snd_soc_component_update_bits(component, AIU_I2S_MISC, |
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AIU_I2S_MISC_HOLD_EN, |
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enable ? AIU_I2S_MISC_HOLD_EN : 0); |
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} |
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static int aiu_encoder_i2s_trigger(struct snd_pcm_substream *substream, int cmd, |
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struct snd_soc_dai *dai) |
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{ |
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struct snd_soc_component *component = dai->component; |
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switch (cmd) { |
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case SNDRV_PCM_TRIGGER_START: |
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case SNDRV_PCM_TRIGGER_RESUME: |
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
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aiu_encoder_i2s_hold(component, false); |
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return 0; |
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case SNDRV_PCM_TRIGGER_STOP: |
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case SNDRV_PCM_TRIGGER_SUSPEND: |
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
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aiu_encoder_i2s_hold(component, true); |
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return 0; |
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default: |
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return -EINVAL; |
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} |
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} |
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static int aiu_encoder_i2s_setup_desc(struct snd_soc_component *component, |
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struct snd_pcm_hw_params *params) |
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{ |
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/* Always operate in split (classic interleaved) mode */ |
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unsigned int desc = AIU_I2S_SOURCE_DESC_MODE_SPLIT; |
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/* Reset required to update the pipeline */ |
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snd_soc_component_write(component, AIU_RST_SOFT, AIU_RST_SOFT_I2S_FAST); |
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snd_soc_component_read(component, AIU_I2S_SYNC); |
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switch (params_physical_width(params)) { |
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case 16: /* Nothing to do */ |
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break; |
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case 32: |
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desc |= (AIU_I2S_SOURCE_DESC_MODE_24BIT | |
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AIU_I2S_SOURCE_DESC_MODE_32BIT); |
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break; |
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default: |
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return -EINVAL; |
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} |
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switch (params_channels(params)) { |
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case 2: /* Nothing to do */ |
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break; |
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case 8: |
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desc |= AIU_I2S_SOURCE_DESC_MODE_8CH; |
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break; |
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default: |
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return -EINVAL; |
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} |
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snd_soc_component_update_bits(component, AIU_I2S_SOURCE_DESC, |
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AIU_I2S_SOURCE_DESC_MODE_8CH | |
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AIU_I2S_SOURCE_DESC_MODE_24BIT | |
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AIU_I2S_SOURCE_DESC_MODE_32BIT | |
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AIU_I2S_SOURCE_DESC_MODE_SPLIT, |
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desc); |
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return 0; |
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} |
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static int aiu_encoder_i2s_set_legacy_div(struct snd_soc_component *component, |
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struct snd_pcm_hw_params *params, |
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unsigned int bs) |
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{ |
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switch (bs) { |
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case 1: |
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case 2: |
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case 4: |
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case 8: |
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/* These are the only valid legacy dividers */ |
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break; |
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default: |
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dev_err(component->dev, "Unsupported i2s divider: %u\n", bs); |
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return -EINVAL; |
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} |
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snd_soc_component_update_bits(component, AIU_CLK_CTRL, |
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AIU_CLK_CTRL_I2S_DIV, |
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FIELD_PREP(AIU_CLK_CTRL_I2S_DIV, |
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__ffs(bs))); |
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snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE, |
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AIU_CLK_CTRL_MORE_I2S_DIV, |
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FIELD_PREP(AIU_CLK_CTRL_MORE_I2S_DIV, |
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0)); |
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return 0; |
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} |
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static int aiu_encoder_i2s_set_more_div(struct snd_soc_component *component, |
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struct snd_pcm_hw_params *params, |
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unsigned int bs) |
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{ |
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/* |
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* NOTE: this HW is odd. |
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* In most configuration, the i2s divider is 'mclk / blck'. |
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* However, in 16 bits - 8ch mode, this factor needs to be |
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* increased by 50% to get the correct output rate. |
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* No idea why ! |
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*/ |
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if (params_width(params) == 16 && params_channels(params) == 8) { |
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if (bs % 2) { |
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dev_err(component->dev, |
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"Cannot increase i2s divider by 50%%\n"); |
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return -EINVAL; |
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} |
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bs += bs / 2; |
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} |
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/* Use CLK_MORE for mclk to bclk divider */ |
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snd_soc_component_update_bits(component, AIU_CLK_CTRL, |
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AIU_CLK_CTRL_I2S_DIV, |
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FIELD_PREP(AIU_CLK_CTRL_I2S_DIV, 0)); |
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snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE, |
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AIU_CLK_CTRL_MORE_I2S_DIV, |
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FIELD_PREP(AIU_CLK_CTRL_MORE_I2S_DIV, |
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bs - 1)); |
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return 0; |
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} |
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static int aiu_encoder_i2s_set_clocks(struct snd_soc_component *component, |
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struct snd_pcm_hw_params *params) |
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{ |
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struct aiu *aiu = snd_soc_component_get_drvdata(component); |
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unsigned int srate = params_rate(params); |
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unsigned int fs, bs; |
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int ret; |
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/* Get the oversampling factor */ |
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fs = DIV_ROUND_CLOSEST(clk_get_rate(aiu->i2s.clks[MCLK].clk), srate); |
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if (fs % 64) |
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return -EINVAL; |
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/* Send data MSB first */ |
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snd_soc_component_update_bits(component, AIU_I2S_DAC_CFG, |
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AIU_I2S_DAC_CFG_MSB_FIRST, |
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AIU_I2S_DAC_CFG_MSB_FIRST); |
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/* Set bclk to lrlck ratio */ |
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snd_soc_component_update_bits(component, AIU_CODEC_DAC_LRCLK_CTRL, |
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AIU_CODEC_DAC_LRCLK_CTRL_DIV, |
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FIELD_PREP(AIU_CODEC_DAC_LRCLK_CTRL_DIV, |
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64 - 1)); |
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bs = fs / 64; |
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if (aiu->platform->has_clk_ctrl_more_i2s_div) |
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ret = aiu_encoder_i2s_set_more_div(component, params, bs); |
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else |
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ret = aiu_encoder_i2s_set_legacy_div(component, params, bs); |
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if (ret) |
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return ret; |
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/* Make sure amclk is used for HDMI i2s as well */ |
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snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE, |
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AIU_CLK_CTRL_MORE_HDMI_AMCLK, |
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AIU_CLK_CTRL_MORE_HDMI_AMCLK); |
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return 0; |
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} |
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static int aiu_encoder_i2s_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *dai) |
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{ |
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struct snd_soc_component *component = dai->component; |
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int ret; |
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/* Disable the clock while changing the settings */ |
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aiu_encoder_i2s_divider_enable(component, false); |
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ret = aiu_encoder_i2s_setup_desc(component, params); |
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if (ret) { |
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dev_err(dai->dev, "setting i2s desc failed\n"); |
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return ret; |
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} |
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ret = aiu_encoder_i2s_set_clocks(component, params); |
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if (ret) { |
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dev_err(dai->dev, "setting i2s clocks failed\n"); |
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return ret; |
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} |
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aiu_encoder_i2s_divider_enable(component, true); |
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return 0; |
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} |
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static int aiu_encoder_i2s_hw_free(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct snd_soc_component *component = dai->component; |
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aiu_encoder_i2s_divider_enable(component, false); |
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return 0; |
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} |
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static int aiu_encoder_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
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{ |
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struct snd_soc_component *component = dai->component; |
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unsigned int inv = fmt & SND_SOC_DAIFMT_INV_MASK; |
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unsigned int val = 0; |
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unsigned int skew; |
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/* Only CPU Master / Codec Slave supported ATM */ |
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if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) |
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return -EINVAL; |
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if (inv == SND_SOC_DAIFMT_NB_IF || |
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inv == SND_SOC_DAIFMT_IB_IF) |
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val |= AIU_CLK_CTRL_LRCLK_INVERT; |
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if (inv == SND_SOC_DAIFMT_IB_NF || |
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inv == SND_SOC_DAIFMT_IB_IF) |
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val |= AIU_CLK_CTRL_AOCLK_INVERT; |
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/* Signal skew */ |
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
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case SND_SOC_DAIFMT_I2S: |
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/* Invert sample clock for i2s */ |
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val ^= AIU_CLK_CTRL_LRCLK_INVERT; |
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skew = 1; |
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break; |
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case SND_SOC_DAIFMT_LEFT_J: |
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skew = 0; |
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break; |
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default: |
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return -EINVAL; |
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} |
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val |= FIELD_PREP(AIU_CLK_CTRL_LRCLK_SKEW, skew); |
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snd_soc_component_update_bits(component, AIU_CLK_CTRL, |
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AIU_CLK_CTRL_LRCLK_INVERT | |
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AIU_CLK_CTRL_AOCLK_INVERT | |
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AIU_CLK_CTRL_LRCLK_SKEW, |
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val); |
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return 0; |
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} |
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static int aiu_encoder_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
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unsigned int freq, int dir) |
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{ |
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struct aiu *aiu = snd_soc_component_get_drvdata(dai->component); |
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int ret; |
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if (WARN_ON(clk_id != 0)) |
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return -EINVAL; |
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if (dir == SND_SOC_CLOCK_IN) |
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return 0; |
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ret = clk_set_rate(aiu->i2s.clks[MCLK].clk, freq); |
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if (ret) |
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dev_err(dai->dev, "Failed to set sysclk to %uHz", freq); |
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return ret; |
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} |
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static const unsigned int hw_channels[] = {2, 8}; |
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static const struct snd_pcm_hw_constraint_list hw_channel_constraints = { |
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.list = hw_channels, |
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.count = ARRAY_SIZE(hw_channels), |
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.mask = 0, |
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}; |
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static int aiu_encoder_i2s_startup(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct aiu *aiu = snd_soc_component_get_drvdata(dai->component); |
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int ret; |
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/* Make sure the encoder gets either 2 or 8 channels */ |
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ret = snd_pcm_hw_constraint_list(substream->runtime, 0, |
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SNDRV_PCM_HW_PARAM_CHANNELS, |
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&hw_channel_constraints); |
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if (ret) { |
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dev_err(dai->dev, "adding channels constraints failed\n"); |
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return ret; |
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} |
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ret = clk_bulk_prepare_enable(aiu->i2s.clk_num, aiu->i2s.clks); |
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if (ret) |
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dev_err(dai->dev, "failed to enable i2s clocks\n"); |
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return ret; |
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} |
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static void aiu_encoder_i2s_shutdown(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct aiu *aiu = snd_soc_component_get_drvdata(dai->component); |
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clk_bulk_disable_unprepare(aiu->i2s.clk_num, aiu->i2s.clks); |
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} |
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const struct snd_soc_dai_ops aiu_encoder_i2s_dai_ops = { |
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.trigger = aiu_encoder_i2s_trigger, |
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.hw_params = aiu_encoder_i2s_hw_params, |
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.hw_free = aiu_encoder_i2s_hw_free, |
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.set_fmt = aiu_encoder_i2s_set_fmt, |
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.set_sysclk = aiu_encoder_i2s_set_sysclk, |
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.startup = aiu_encoder_i2s_startup, |
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.shutdown = aiu_encoder_i2s_shutdown, |
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}; |
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