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567 lines
14 KiB
567 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2010, Lars-Peter Clausen <[email protected]> |
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*/ |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/dma-mapping.h> |
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#include <sound/core.h> |
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#include <sound/pcm.h> |
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#include <sound/pcm_params.h> |
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#include <sound/soc.h> |
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#include <sound/initval.h> |
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#include <sound/dmaengine_pcm.h> |
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#include "jz4740-i2s.h" |
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#define JZ_REG_AIC_CONF 0x00 |
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#define JZ_REG_AIC_CTRL 0x04 |
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#define JZ_REG_AIC_I2S_FMT 0x10 |
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#define JZ_REG_AIC_FIFO_STATUS 0x14 |
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#define JZ_REG_AIC_I2S_STATUS 0x1c |
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#define JZ_REG_AIC_CLK_DIV 0x30 |
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#define JZ_REG_AIC_FIFO 0x34 |
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#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12) |
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#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf << 8) |
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#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) |
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#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) |
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#define JZ_AIC_CONF_I2S BIT(4) |
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#define JZ_AIC_CONF_RESET BIT(3) |
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#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2) |
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#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) |
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#define JZ_AIC_CONF_ENABLE BIT(0) |
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#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12 |
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#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8 |
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#define JZ4760_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 24 |
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#define JZ4760_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 16 |
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#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19) |
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#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16) |
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#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) |
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#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) |
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#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) |
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#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10) |
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#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9) |
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#define JZ_AIC_CTRL_FLUSH BIT(8) |
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#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6) |
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#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5) |
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#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4) |
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#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3) |
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#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2) |
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#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) |
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#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) |
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#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19 |
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#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16 |
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#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) |
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#define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) |
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#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) |
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#define JZ_AIC_I2S_FMT_MSB BIT(0) |
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#define JZ_AIC_I2S_STATUS_BUSY BIT(2) |
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#define JZ_AIC_CLK_DIV_MASK 0xf |
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#define I2SDIV_DV_SHIFT 0 |
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#define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT) |
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#define I2SDIV_IDV_SHIFT 8 |
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#define I2SDIV_IDV_MASK (0xf << I2SDIV_IDV_SHIFT) |
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enum jz47xx_i2s_version { |
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JZ_I2S_JZ4740, |
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JZ_I2S_JZ4760, |
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JZ_I2S_JZ4770, |
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JZ_I2S_JZ4780, |
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}; |
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struct i2s_soc_info { |
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enum jz47xx_i2s_version version; |
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struct snd_soc_dai_driver *dai; |
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}; |
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struct jz4740_i2s { |
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struct resource *mem; |
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void __iomem *base; |
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dma_addr_t phys_base; |
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struct clk *clk_aic; |
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struct clk *clk_i2s; |
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struct snd_dmaengine_dai_dma_data playback_dma_data; |
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struct snd_dmaengine_dai_dma_data capture_dma_data; |
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const struct i2s_soc_info *soc_info; |
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}; |
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static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s, |
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unsigned int reg) |
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{ |
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return readl(i2s->base + reg); |
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} |
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static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s, |
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unsigned int reg, uint32_t value) |
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{ |
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writel(value, i2s->base + reg); |
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} |
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static int jz4740_i2s_startup(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
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uint32_t conf, ctrl; |
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int ret; |
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if (snd_soc_dai_active(dai)) |
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return 0; |
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ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); |
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ctrl |= JZ_AIC_CTRL_FLUSH; |
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jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); |
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ret = clk_prepare_enable(i2s->clk_i2s); |
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if (ret) |
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return ret; |
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conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); |
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conf |= JZ_AIC_CONF_ENABLE; |
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); |
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return 0; |
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} |
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static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
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uint32_t conf; |
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if (snd_soc_dai_active(dai)) |
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return; |
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conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); |
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conf &= ~JZ_AIC_CONF_ENABLE; |
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); |
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clk_disable_unprepare(i2s->clk_i2s); |
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} |
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static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd, |
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struct snd_soc_dai *dai) |
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{ |
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struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
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uint32_t ctrl; |
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uint32_t mask; |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
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mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA; |
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else |
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mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA; |
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ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); |
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switch (cmd) { |
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case SNDRV_PCM_TRIGGER_START: |
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case SNDRV_PCM_TRIGGER_RESUME: |
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
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ctrl |= mask; |
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break; |
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case SNDRV_PCM_TRIGGER_STOP: |
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case SNDRV_PCM_TRIGGER_SUSPEND: |
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
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ctrl &= ~mask; |
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break; |
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default: |
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return -EINVAL; |
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} |
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jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); |
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return 0; |
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} |
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static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
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{ |
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struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
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uint32_t format = 0; |
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uint32_t conf; |
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conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); |
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conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER); |
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
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case SND_SOC_DAIFMT_CBS_CFS: |
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conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER; |
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format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK; |
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break; |
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case SND_SOC_DAIFMT_CBM_CFS: |
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conf |= JZ_AIC_CONF_SYNC_CLK_MASTER; |
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break; |
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case SND_SOC_DAIFMT_CBS_CFM: |
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conf |= JZ_AIC_CONF_BIT_CLK_MASTER; |
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break; |
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case SND_SOC_DAIFMT_CBM_CFM: |
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break; |
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default: |
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return -EINVAL; |
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} |
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
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case SND_SOC_DAIFMT_MSB: |
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format |= JZ_AIC_I2S_FMT_MSB; |
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break; |
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case SND_SOC_DAIFMT_I2S: |
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break; |
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default: |
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return -EINVAL; |
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} |
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
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case SND_SOC_DAIFMT_NB_NF: |
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break; |
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default: |
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return -EINVAL; |
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} |
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); |
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jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format); |
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return 0; |
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} |
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static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) |
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{ |
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struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
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unsigned int sample_size; |
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uint32_t ctrl, div_reg; |
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int div; |
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ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); |
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div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV); |
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div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params)); |
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switch (params_format(params)) { |
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case SNDRV_PCM_FORMAT_S8: |
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sample_size = 0; |
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break; |
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case SNDRV_PCM_FORMAT_S16: |
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sample_size = 1; |
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break; |
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default: |
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return -EINVAL; |
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} |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
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ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK; |
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ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET; |
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if (params_channels(params) == 1) |
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ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO; |
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else |
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ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO; |
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div_reg &= ~I2SDIV_DV_MASK; |
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div_reg |= (div - 1) << I2SDIV_DV_SHIFT; |
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} else { |
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ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK; |
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ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET; |
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if (i2s->soc_info->version >= JZ_I2S_JZ4770) { |
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div_reg &= ~I2SDIV_IDV_MASK; |
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div_reg |= (div - 1) << I2SDIV_IDV_SHIFT; |
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} else { |
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div_reg &= ~I2SDIV_DV_MASK; |
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div_reg |= (div - 1) << I2SDIV_DV_SHIFT; |
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} |
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} |
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jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); |
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jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg); |
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return 0; |
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} |
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static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
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unsigned int freq, int dir) |
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{ |
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struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
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struct clk *parent; |
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int ret = 0; |
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switch (clk_id) { |
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case JZ4740_I2S_CLKSRC_EXT: |
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parent = clk_get(NULL, "ext"); |
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if (IS_ERR(parent)) |
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return PTR_ERR(parent); |
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clk_set_parent(i2s->clk_i2s, parent); |
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break; |
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case JZ4740_I2S_CLKSRC_PLL: |
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parent = clk_get(NULL, "pll half"); |
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if (IS_ERR(parent)) |
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return PTR_ERR(parent); |
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clk_set_parent(i2s->clk_i2s, parent); |
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ret = clk_set_rate(i2s->clk_i2s, freq); |
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break; |
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default: |
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return -EINVAL; |
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} |
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clk_put(parent); |
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return ret; |
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} |
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static int jz4740_i2s_suspend(struct snd_soc_component *component) |
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{ |
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struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); |
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uint32_t conf; |
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if (snd_soc_component_active(component)) { |
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conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); |
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conf &= ~JZ_AIC_CONF_ENABLE; |
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); |
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clk_disable_unprepare(i2s->clk_i2s); |
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} |
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clk_disable_unprepare(i2s->clk_aic); |
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return 0; |
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} |
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static int jz4740_i2s_resume(struct snd_soc_component *component) |
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{ |
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struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); |
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uint32_t conf; |
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int ret; |
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ret = clk_prepare_enable(i2s->clk_aic); |
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if (ret) |
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return ret; |
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if (snd_soc_component_active(component)) { |
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ret = clk_prepare_enable(i2s->clk_i2s); |
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if (ret) { |
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clk_disable_unprepare(i2s->clk_aic); |
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return ret; |
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} |
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conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); |
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conf |= JZ_AIC_CONF_ENABLE; |
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); |
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} |
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return 0; |
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} |
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static void jz4740_i2c_init_pcm_config(struct jz4740_i2s *i2s) |
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{ |
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struct snd_dmaengine_dai_dma_data *dma_data; |
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/* Playback */ |
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dma_data = &i2s->playback_dma_data; |
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dma_data->maxburst = 16; |
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dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO; |
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/* Capture */ |
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dma_data = &i2s->capture_dma_data; |
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dma_data->maxburst = 16; |
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dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO; |
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} |
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static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) |
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{ |
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struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
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uint32_t conf; |
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int ret; |
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ret = clk_prepare_enable(i2s->clk_aic); |
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if (ret) |
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return ret; |
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jz4740_i2c_init_pcm_config(i2s); |
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snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data, |
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&i2s->capture_dma_data); |
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if (i2s->soc_info->version >= JZ_I2S_JZ4760) { |
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conf = (7 << JZ4760_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) | |
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(8 << JZ4760_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) | |
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JZ_AIC_CONF_OVERFLOW_PLAY_LAST | |
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JZ_AIC_CONF_I2S | |
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JZ_AIC_CONF_INTERNAL_CODEC; |
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} else { |
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conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) | |
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(8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) | |
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JZ_AIC_CONF_OVERFLOW_PLAY_LAST | |
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JZ_AIC_CONF_I2S | |
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JZ_AIC_CONF_INTERNAL_CODEC; |
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} |
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET); |
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); |
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return 0; |
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} |
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static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai) |
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{ |
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struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
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clk_disable_unprepare(i2s->clk_aic); |
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return 0; |
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} |
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static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = { |
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.startup = jz4740_i2s_startup, |
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.shutdown = jz4740_i2s_shutdown, |
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.trigger = jz4740_i2s_trigger, |
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.hw_params = jz4740_i2s_hw_params, |
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.set_fmt = jz4740_i2s_set_fmt, |
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.set_sysclk = jz4740_i2s_set_sysclk, |
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}; |
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#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \ |
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SNDRV_PCM_FMTBIT_S16_LE) |
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static struct snd_soc_dai_driver jz4740_i2s_dai = { |
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.probe = jz4740_i2s_dai_probe, |
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.remove = jz4740_i2s_dai_remove, |
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.playback = { |
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.channels_min = 1, |
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.channels_max = 2, |
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.rates = SNDRV_PCM_RATE_8000_48000, |
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.formats = JZ4740_I2S_FMTS, |
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}, |
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.capture = { |
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.channels_min = 2, |
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.channels_max = 2, |
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.rates = SNDRV_PCM_RATE_8000_48000, |
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.formats = JZ4740_I2S_FMTS, |
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}, |
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.symmetric_rate = 1, |
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.ops = &jz4740_i2s_dai_ops, |
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}; |
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static const struct i2s_soc_info jz4740_i2s_soc_info = { |
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.version = JZ_I2S_JZ4740, |
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.dai = &jz4740_i2s_dai, |
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}; |
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static const struct i2s_soc_info jz4760_i2s_soc_info = { |
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.version = JZ_I2S_JZ4760, |
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.dai = &jz4740_i2s_dai, |
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}; |
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static struct snd_soc_dai_driver jz4770_i2s_dai = { |
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.probe = jz4740_i2s_dai_probe, |
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.remove = jz4740_i2s_dai_remove, |
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.playback = { |
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.channels_min = 1, |
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.channels_max = 2, |
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.rates = SNDRV_PCM_RATE_8000_48000, |
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.formats = JZ4740_I2S_FMTS, |
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}, |
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.capture = { |
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.channels_min = 2, |
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.channels_max = 2, |
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.rates = SNDRV_PCM_RATE_8000_48000, |
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.formats = JZ4740_I2S_FMTS, |
|
}, |
|
.ops = &jz4740_i2s_dai_ops, |
|
}; |
|
|
|
static const struct i2s_soc_info jz4770_i2s_soc_info = { |
|
.version = JZ_I2S_JZ4770, |
|
.dai = &jz4770_i2s_dai, |
|
}; |
|
|
|
static const struct i2s_soc_info jz4780_i2s_soc_info = { |
|
.version = JZ_I2S_JZ4780, |
|
.dai = &jz4770_i2s_dai, |
|
}; |
|
|
|
static const struct snd_soc_component_driver jz4740_i2s_component = { |
|
.name = "jz4740-i2s", |
|
.suspend = jz4740_i2s_suspend, |
|
.resume = jz4740_i2s_resume, |
|
}; |
|
|
|
static const struct of_device_id jz4740_of_matches[] = { |
|
{ .compatible = "ingenic,jz4740-i2s", .data = &jz4740_i2s_soc_info }, |
|
{ .compatible = "ingenic,jz4760-i2s", .data = &jz4760_i2s_soc_info }, |
|
{ .compatible = "ingenic,jz4770-i2s", .data = &jz4770_i2s_soc_info }, |
|
{ .compatible = "ingenic,jz4780-i2s", .data = &jz4780_i2s_soc_info }, |
|
{ /* sentinel */ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, jz4740_of_matches); |
|
|
|
static int jz4740_i2s_dev_probe(struct platform_device *pdev) |
|
{ |
|
struct device *dev = &pdev->dev; |
|
struct jz4740_i2s *i2s; |
|
struct resource *mem; |
|
int ret; |
|
|
|
i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL); |
|
if (!i2s) |
|
return -ENOMEM; |
|
|
|
i2s->soc_info = device_get_match_data(dev); |
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
i2s->base = devm_ioremap_resource(dev, mem); |
|
if (IS_ERR(i2s->base)) |
|
return PTR_ERR(i2s->base); |
|
|
|
i2s->phys_base = mem->start; |
|
|
|
i2s->clk_aic = devm_clk_get(dev, "aic"); |
|
if (IS_ERR(i2s->clk_aic)) |
|
return PTR_ERR(i2s->clk_aic); |
|
|
|
i2s->clk_i2s = devm_clk_get(dev, "i2s"); |
|
if (IS_ERR(i2s->clk_i2s)) |
|
return PTR_ERR(i2s->clk_i2s); |
|
|
|
platform_set_drvdata(pdev, i2s); |
|
|
|
ret = devm_snd_soc_register_component(dev, &jz4740_i2s_component, |
|
i2s->soc_info->dai, 1); |
|
if (ret) |
|
return ret; |
|
|
|
return devm_snd_dmaengine_pcm_register(dev, NULL, |
|
SND_DMAENGINE_PCM_FLAG_COMPAT); |
|
} |
|
|
|
static struct platform_driver jz4740_i2s_driver = { |
|
.probe = jz4740_i2s_dev_probe, |
|
.driver = { |
|
.name = "jz4740-i2s", |
|
.of_match_table = jz4740_of_matches, |
|
}, |
|
}; |
|
|
|
module_platform_driver(jz4740_i2s_driver); |
|
|
|
MODULE_AUTHOR("Lars-Peter Clausen, <[email protected]>"); |
|
MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver"); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_ALIAS("platform:jz4740-i2s");
|
|
|